From nobody Sun May 5 13:44:22 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org; Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1489927881324300.72593977603844; Sun, 19 Mar 2017 05:51:21 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1cpaIZ-0001bO-MM; Sun, 19 Mar 2017 13:51:03 +0100 Received: from mxb2.seznam.cz ([77.75.76.89]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.86_2) (envelope-from ) id 1cpaIO-0001aH-00 for seabios@seabios.org; Sun, 19 Mar 2017 13:51:01 +0100 Received: from email.seznam.cz by email-smtpc13a.ng.seznam.cz (email-smtpc13a.ng.seznam.cz [10.23.11.135]) id 554d0b788530b6a551f34637; Sun, 19 Mar 2017 13:50:49 +0100 (CET) Received: from unknown ([::ffff:94.78.181.79]) by email.seznam.cz (szn-ebox-4.5.223) with HTTP; Sun, 19 Mar 2017 13:50:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=email.cz; s=beta; t=1489927849; bh=WMmB2ePc7wycS/gtAse0xjrZJvvtsdbuQ2Dh+PtF0Go=; h=Received:From:To:Subject:Date:Message-Id:Mime-Version:X-Mailer: Content-Type:Content-Transfer-Encoding; b=gpHix1Rg/7YSKk3V3oN6UA4mzG4qsxDDU/nuG3qu8EjRyXT36PB6NfDapLwsbGluP ZOwzLK4n1UtUz0G1uJthxye/AUMr/S+/rRThVRXpRaGofXzLSiKKFaKOdzWzSVS/zd YfdGJPsF3YfC39S7FgGabGM2dWgQp1UUP/xXlKgk= From: To: Date: Sun, 19 Mar 2017 13:50:47 +0100 (CET) Message-Id: <2GM.4larv.5I6lv0KJ{Gh.1Opdwd@seznam.cz> Mime-Version: 1.0 (szn-mime-2.0.14) X-Mailer: szn-ebox-4.5.223 X-Spam-Score: 0.3 (/) Subject: [SeaBIOS] [Bochs] [PATCH RFC] shadow: Change order of PCI writes X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" I am working on an issue with SeaBIOS running in Bochs emulator. I found I need to revert SeaBIOS patch d449a11, otherwise Bochs freezes. After the further investigation, I narrowed down the problem to those lines: File: src/fw/shadow.c Function: __make_bios_writable_intel 48 // Write PAM settings back to pci config space 49 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); 50 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); File: src/fw/shadow.c Function: make_bios_readonly_intel 109 // Write PAM settings back to pci config space 110 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); 111 pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); What has changed, comparing to the code before patch d449a11 is the order of writes to PAM registers. Before d449a11 the order was: 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x59 After d449a11 the order is : 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f I believe also the 0x58 (DRAMT?) register is written after the patch d449a11 and was not before. I checked, and the registers values after write are exactly the same in both cases (before/after patch). This lead me to think the order of writes matters. So I prepared the patch that restores the old order. I works well and fixes the issue with Bochs. But there is still one think I cannot explain and I hope I can find some help here. If you look on the patch below, you will see I had to use different pci write functions in __make_bios_writable_intel and make_bios_readonly_intel. The only difference in those functions (I think) is the size of data that is written at one call. Still It does not work for me when written some other way. Again, I would appreciate if someone could explain it to me or point me some documentation. Just to summarize, I have two questions: 1. Why the order of pci writes makes a difference here? 2. Why the size of pci writes matters? From 953c133a6ade49e9148a0734ffefc0fb27c116fb Mon Sep 17 00:00:00 2001 From: Petr Berky Date: Sun, 19 Mar 2017 10:14:49 +0100 Subject: [PATCH RFC] shadow: Change order of PCI writes This change solves the problem with Bochs freeze --- src/fw/shadow.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/fw/shadow.c b/src/fw/shadow.c index c80b266..508af20 100644 --- a/src/fw/shadow.c +++ b/src/fw/shadow.c @@ -23,6 +23,7 @@ =20 union pamdata_u { u8 data8[8]; + u16 data16[4]; u32 data32[2]; }; =20 @@ -46,8 +47,9 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) pam[0] =3D 0x30; =20 // Write PAM settings back to pci config space - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); + pci_config_writew(bdf, ALIGN_DOWN(pam0, 4) + 2, pamdata.data16[1]); pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 1, pamdata.data8[1]); =20 if (!ram_present) // Copy bios. @@ -107,8 +109,11 @@ make_bios_readonly_intel(u16 bdf, u32 pam0) pam[0] =3D 0x10; =20 // Write PAM settings back to pci config space - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); - pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); + pci_config_writew(bdf, ALIGN_DOWN(pam0, 4) + 2, pamdata.data16[1]); + pci_config_writew(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data16[2]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 6, pamdata.data8[6]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 7, pamdata.data8[7]); + pci_config_writeb(bdf, ALIGN_DOWN(pam0, 4) + 1, pamdata.data8[1]); } =20 static int ShadowBDF =3D -1; --=20 2.11.0 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://www.coreboot.org/mailman/listinfo/seabios