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no-senders; approved; loop; banned-address; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; emergency; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header Cc: Gerd Hoffmann X-Mailman-Version: 3.3.11b1 Precedence: list Subject: [SeaBIOS] [PATCH 1/3] clext: report the chip id that was read at init time List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: --- X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1792304141190158500 Content-Type: text/plain; charset="utf-8" clext_101280() (int 10h, ax=3D12xxh, bl=3D80h, "inquire VGA type") reads CR27 on each call and reports 0xff for a value it does not know. This fails when the call comes from a DOS session in a window under OS/2 2.1, before the Cirrus display driver is installed: OS/2 virtualizes the VGA ports of such a session, and the read of CR27 does not return the chip id. The OS/2 display driver package "Cirrus Logic 5436 v1.14" for the CL-GD5436/46 (1996) checks the chip with IDCHIP.EXE in such a session and accepts only 0x36 or 0x39. On OS/2 2.1 with QEMU's cirrus-vga (CL-GD5446) and SeaVGABIOS, IDCHIP prints "Chiptype is 0xff", and the installer stops with "5436/5446 not detected". In a full screen session IDCHIP gets 0x39. The Cirrus BIOS also reads CR27 at run time, but it reports a CL-GD5436 (0x36) for any value it does not know (CL-GD5436/46 PCI VGA BIOS 1.25, code at offset 0xc34). So with this BIOS the installer should accept the chip; I see this in the code, I did not test it. Read CR27 once in clext_setup(), as is already done for the memory size that clext_101285() reports, and report the stored value. The chip does not change while the machine runs. With this patch IDCHIP prints "Chiptype is 0x39" in the window as well. Signed-off-by: Christian Quante --- vgasrc/clext.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/vgasrc/clext.c b/vgasrc/clext.c index c89a47b4..0aaf04bd 100644 --- a/vgasrc/clext.c +++ b/vgasrc/clext.c @@ -465,10 +465,15 @@ clext_set_mode(struct vgamode_s *vmode_g, int flags) * extbios ****************************************************************/ =20 +// Chip id (CR27), read once in clext_setup(). A DOS session under +// OS/2 can call int 10h with the VGA ports virtualized, so a later read +// of CR27 may not return the chip id. +static u8 cirrus_chip_id VAR16; + static void clext_101280(struct bregs *regs) { - u8 v =3D stdvga_crtc_read(stdvga_get_crtc(), 0x27); + u8 v =3D GET_GLOBAL(cirrus_chip_id); if (v =3D=3D 0xa0) // 5430 regs->ax =3D 0x0032; @@ -622,6 +627,7 @@ clext_setup(void) u16 totalmem =3D cirrus_get_memsize(); SET_VGA(VBE_total_memory, totalmem * 64 * 1024); SET_VGA(VBE_win_granularity, 16); + SET_VGA(cirrus_chip_id, stdvga_crtc_read(stdvga_get_crtc(), 0x27)); =20 return 0; } --=20 2.53.0 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org From nobody Tue Oct 20 00:16:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; 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Sun, 18 Oct 2026 07:20:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quante.one; s=cloudpit; t=1792300813; bh=0xdM7iTCUFqdi3hjH4qaHRRjDXgQwsDb+dB4b5AJeto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iUWHLzaRlMCgDRo5tDRAEnedPvjJgRhTy1gGhUoRnu0gMDfWVmM1ZX//OTilNtKc3 t4MNykppTVQbgryqOF5z40DsdVlcKV6LqkdSKe0nFeJB6dhHkzMHg7nKVy+U1JhITI VQgwVy8Csa+QbChhJitRSxi+szUXWOC1zUKh8cS4= X-SecureMailgate-Identity: christian@quante.one;web279.dogado.net From: Christian Quante To: seabios@seabios.org Date: Sun, 18 Oct 2026 07:19:46 +0200 Message-ID: <20261018051949.12563-3-christian@quante.one> In-Reply-To: <20261018051949.12563-1-christian@quante.one> References: <20261018051949.12563-1-christian@quante.one> MIME-Version: 1.0 X-PPP-Message-ID: <179230081347.407899.11458448848621937239@web279.dogado.net> X-PPP-Vhost: quante.one X-SecureMailgate-Domain: web279.dogado.net X-SecureMailgate-Username: 31.47.255.59 X-SecureMailgate-Outgoing-Class: ham X-SecureMailgate-Outgoing-Evidence: SB/global_tokens (0.000164007631659) X-Recommended-Action: accept X-Filter-ID: 9kzQTOBWQUFZTohSKvQbgI7ZDo5ubYELi59AwcWUnuX3pf3QdpS1fVXteL9BT8acxmDVvAbpkZk7 JZIi/Fcv3Cu2SmbhJN1U9FKs8X3+Nt1HOctZ5X+40a9IXddeG3M38JQYgcgjsac3uQcQdCX4ROfH zJ6mVE7ewsipSVIfs4a/yRXRbPFTt3ZHCuPnIxpfS5+h1uiHzk/Rfxfh461YLyu3RZI1CD15pCOE 1vk99RMgoMVb7lebWWPLzvZvEUCPdOtYechJ/ikE1WgRg4cS6A6B6pTstltS07kaQJ8I9sYal0h7 43VOpKNY+4MjijihZK0EMmf3P50Ajf/tIX00Fuu2beRqilmjgQ6jA3UwYgm3QTha208ypFqQwBFb xm4JX7semJdl8Weuy8+tlMSTQwhoy9D5QZ6a84vJal7pM1XhlAOd290vPXa7Loma0jth7qAXzi6H u+vd1PUHqD56sKVpCSy8DvYjml2C5x08HjVOdbycUIjxTi/oScdKqdkqU23mck4kYaL7W/YjuX9F gtaPrsMji/nLJj58tIE9bJtlIqecxOBP1yJf91UNzkSEUDq6mKQ/XAiI42Mzh38yXz3dKxLhoxcm aInYbR5vlqHlDhVAB/0EYD/jnz2OZJv6szlVwj1n2JAvHUSGQgae904HZe+Npbm5PA9zxaDCuu7n enbrzWUw2X62ZQfetBN+Wd6yNxOSUIsmGCJDuSiGSNdj68Lf4FNI5GmjYNknO4X1WwpSOxYAbinP WCPuFtl/z3TkCVxFNHhnmJsZcsfsRn+Ccb8wDY4fh+1g1AuTVI49tQrhDVxWCGj1JArKPJWkG7EB ouE/Lp65oEK6Kr4PFISAzVaFNHfkjGyFyiRzr7YOhfiboNBv0POUVLQJNXGP/GGMrN0VgEP1fddi hPZrzx1Lw2yMf4vpvhlM+vErQ1gn6IjLLbcvolUaG2pSKCEkiWrFfcvTzpdI3AEG059XQe3NdBcE yGlzikJRHOzWVtB3OnKG9eRDP2/Ogb+c8D2oSvdcBJ1869L2y5ERFHC8NPIK4B7OUVSn0kbL6D23 dfd3aH2fATPqEIe+zbt2NwyT7DYzFfTn4NXnBjEun9DvZ0n9a1rfFCnSMsc+vEwrNstTbe4wBw6S kC2jAENWaINDgXBbKTIlqNpRK89muFbKwBsa9A+nmEd7cRVfyxrpZ1WT35ix5VehBc2cUR742vO7 eUcOGCmJTaorUhtlNRknxw== X-Report-Abuse-To: spam@node04.secure-mailgate.com X-Complaints-To: abuse@node01.secure-mailgate.com Message-ID-Hash: BZRWAENTB5XXZC2L3TFAVKW2KSWROAHF X-Message-ID-Hash: BZRWAENTB5XXZC2L3TFAVKW2KSWROAHF X-MailFrom: christian@quante.one X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; loop; banned-address; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; emergency; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header Cc: Gerd Hoffmann X-Mailman-Version: 3.3.11b1 Precedence: list Subject: [SeaBIOS] [PATCH 2/3] clext: set the bank granularity per mode, as the Cirrus BIOS does List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: --- X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1792303662365158500 Content-Type: text/plain; charset="utf-8" clext_set_mode() sets 16K bank granularity (GR0B bit 5) for the Cirrus modes (only a VBE mode set with a linear frame buffer and without clearing the memory leaves the bit clear), and vbe_104f01() reports a window granularity of 16K for every mode. In my measurements, the Cirrus BIOS uses 16K only for the modes that need more than 1MB. Smaller modes get 4K units (GR0B bit 5 clear); the 8 bits of GR9 still reach all of such a mode. GR0B bit 5 after a mode set, measured on QEMU with the original BIOS as option ROM (CL-GD5436/46 PCI VGA BIOS 1.25 on cirrus-vga, CL-GD543x VGA BIOS 1.00a on isa-cirrus-vga, same results; I did not measure the 15-bit and 24-bit modes): int 10h ah=3D00h 5fh 5ch 60h 64h clear 6dh 74h set VBE 4f02h 101h 103h 105h 111h 114h clear, 4f01h reports 4K 107h 117h set, 4f01h reports 16K SeaVGABIOS sets the bit for all of them and reports 16K. (A Diamond SpeedStar BIOS for the CL-GD543x uses 16K for 101h, 103h and 105h, and reports 16K for them.) Software that sets a mode through the BIOS and then switches banks by itself depends on this. Set the granularity at the end of clext_set_mode() from the size of the mode, and report the same value in vbe_104f01() through a new function vgahw_get_win_granularity(). With this patch, the 13 mode sets above give the same GR0B, the same reported granularity and the same GR9 after 4f05h as with the Cirrus BIOS. Signed-off-by: Christian Quante --- Notes: Seen with the SVGA support of OS/2 2.1 ("SVGA ON"): it records the register state after each mode set in SVGADATA.PMI, and later writes GR9 in 4K units. With SeaVGABIOS it records GR0B =3D 0x20 for the 256 color modes, and the desktop at 1024x768 comes out in bands; with this patch it records GR0B =3D 0x00, and the desktop is correct. OS/2 2.1 knows only the CL-GD5422, CL-GD5424 and CL-GD5426, so I saw this with a local QEMU build in which isa-cirrus-vga reports a CL-GD5426. OS/2 also needs the QEMU patch "hw/display/cirrus_vga: read back the cursor position bits of SR10/SR11" to find the Cirrus chip; I will send it to qemu-devel soon. vgasrc/clext.c | 21 ++++++++++++++++----- vgasrc/vbe.c | 2 +- vgasrc/vgahw.h | 6 ++++++ vgasrc/vgautil.h | 1 + 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/vgasrc/clext.c b/vgasrc/clext.c index 0aaf04bd..4d34bc44 100644 --- a/vgasrc/clext.c +++ b/vgasrc/clext.c @@ -323,6 +323,18 @@ clext_set_window(struct vgamode_s *curmode_g, int wind= ow, int val) return 0; } =20 +// Bank granularity in KB, as the Cirrus BIOS sets it: GR9 addresses +// 1MB in 4K units, so only larger modes use 16K units. +int +clext_get_win_granularity(struct vgamode_s *vmode_g) +{ + if (!is_cirrus_mode(vmode_g)) + return GET_GLOBAL(VBE_win_granularity); + u32 size =3D (u32)GET_GLOBAL(vmode_g->width) * GET_GLOBAL(vmode_g->hei= ght) + * DIV_ROUND_UP(GET_GLOBAL(vmode_g->depth), 8); + return size > 1024 * 1024 ? 16 : 4; +} + int clext_get_linelength(struct vgamode_s *curmode_g) { @@ -421,15 +433,15 @@ cirrus_switch_mode(struct cirrus_mode_s *table) } =20 static void -cirrus_enable_16k_granularity(void) +cirrus_set_granularity(int kb) { - stdvga_grdc_mask(0x0b, 0x00, 0x20); + stdvga_grdc_mask(0x0b, 0x20, kb =3D=3D 16 ? 0x20 : 0x00); } =20 static void cirrus_clear_vram(u16 fill) { - cirrus_enable_16k_granularity(); + cirrus_set_granularity(16); int count =3D GET_GLOBAL(VBE_total_memory) / (16 * 1024); int i; for (i=3D0; imemmodel) =3D=3D MM_PACKED && !(flags & MF_NOP= ALETTE)) stdvga_set_packed_palette(); - if (!(flags & MF_LINEARFB)) - cirrus_enable_16k_granularity(); if (!(flags & MF_NOCLEARMEM)) // fill with 0xff to keep win 2K happy cirrus_clear_vram(flags & MF_LEGACY ? 0xffff : 0x0000); + cirrus_set_granularity(clext_get_win_granularity(vmode_g)); return 0; } =20 diff --git a/vgasrc/vbe.c b/vgasrc/vbe.c index 67162d97..0bd8be53 100644 --- a/vgasrc/vbe.c +++ b/vgasrc/vbe.c @@ -94,7 +94,7 @@ vbe_104f01(struct bregs *regs) memset_far(seg, info, 0, sizeof(*info)); =20 // Basic information about video controller. - u32 win_granularity =3D GET_GLOBAL(VBE_win_granularity); + u32 win_granularity =3D vgahw_get_win_granularity(vmode_g); SET_FARVAR(seg, info->winA_attributes, (win_granularity ? VBE_WINDOW_ATTRIBUTE_RELOCATABLE : 0) | VBE_WINDOW_ATTRIBUTE_READABLE | diff --git a/vgasrc/vgahw.h b/vgasrc/vgahw.h index a6ddaa95..86a76623 100644 --- a/vgasrc/vgahw.h +++ b/vgasrc/vgahw.h @@ -85,6 +85,12 @@ static inline int vgahw_set_window(struct vgamode_s *cur= mode_g, int window return stdvga_set_window(curmode_g, window, val); } =20 +static inline int vgahw_get_win_granularity(struct vgamode_s *vmode_g) { + if (CONFIG_VGA_CIRRUS) + return clext_get_win_granularity(vmode_g); + return GET_GLOBAL(VBE_win_granularity); +} + static inline int vgahw_get_linelength(struct vgamode_s *curmode_g) { if (CONFIG_VGA_CIRRUS) return clext_get_linelength(curmode_g); diff --git a/vgasrc/vgautil.h b/vgasrc/vgautil.h index ea1ac772..d0780dfb 100644 --- a/vgasrc/vgautil.h +++ b/vgasrc/vgautil.h @@ -32,6 +32,7 @@ struct vgamode_s *clext_find_mode(int mode); void clext_list_modes(u16 seg, u16 *dest, u16 *last); int clext_get_window(struct vgamode_s *curmode_g, int window); int clext_set_window(struct vgamode_s *curmode_g, int window, int val); +int clext_get_win_granularity(struct vgamode_s *vmode_g); int clext_get_linelength(struct vgamode_s *curmode_g); int clext_set_linelength(struct vgamode_s *curmode_g, int val); int clext_get_displaystart(struct vgamode_s *curmode_g); --=20 2.53.0 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org From nobody Tue Oct 20 00:16:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from coreboot.org (mail.coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 1792302247549916.8434208370212; Sat, 17 Oct 2026 22:44:07 -0700 (PDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id 6685B54E2F0; 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no-senders; approved; loop; banned-address; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; emergency; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header Cc: Gerd Hoffmann X-Mailman-Version: 3.3.11b1 Precedence: list Subject: [SeaBIOS] [PATCH 3/3] clext: leave the hardware cursor off and at 32x32 after a mode set List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: --- X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1792302250452158500 Content-Type: text/plain; charset="utf-8" The tables of the Cirrus modes write 0x04 to SR12 (graphics cursor attribute), which selects the 64x64 cursor. The Cirrus BIOS writes 0x00 to SR12 and SR13 on each mode set that I measured, for the Cirrus modes and for the standard VGA modes. SR12 and SR13 after a mode set, with other values written before (SR12 =3D 0x04 or 0x05, SR13 =3D 0x2a), measured on QEMU with the original BIOS as option ROM (CL-GD5436/46 PCI VGA BIOS 1.25 on cirrus-vga, CL-GD543x VGA BIOS 1.00a and Diamond SpeedStar BIOS 1.00 on isa-cirrus-vga, same results): SR12 SR13 int 10h ah=3D00h 03h 12h 13h 5fh 5ch 60h 64h 6dh 74h 00h 00h VBE 4f02h 101h 103h 105h 107h 111h 114h 117h 00h 00h SeaVGABIOS leaves SR12 04h, SR13 00h after the Cirrus modes, and keeps the values from before for the standard VGA modes. A display driver that changes only some bits of SR12 depends on this. The Windows 3.1 drivers for WIN-OS/2 full screen sessions in OS/2 Warp 3 ("Cirrus Logic GD5426/28/29/3x FULLSCREEN WINDOWS DRIVER", 64K_1024.DRV and 256_1280.DRV) draw the mouse pointer with the hardware cursor: they write a 32x32 pattern, select it with SR13 =3D 0x3e, and set bit 0 of SR12 with a read-modify-write. (They set bit 1 only for a short time, to load the cursor colors into the DAC.) After a mode set by SeaVGABIOS, bit 2 stays set, so the card shows a 64x64 cursor and takes its pattern from another place in video memory. Write 0x00 to SR12 in the tables of the Cirrus modes, and write 0x00 to SR12 and SR13 when switching back to a standard VGA mode. With this patch the mode sets above give the same SR12 and SR13 as with the Cirrus BIOS. Signed-off-by: Christian Quante --- Notes: Seen in OS/2 Warp 3 on QEMU's isa-cirrus-vga, in a WIN-OS/2 full screen session: the mouse pointer is a white block of 64x64 pixels with some loose pixels in it, instead of the arrow. With this patch it is the arrow. Warp 3 with its Cirrus driver needs the QEMU patch "hw/display/cirrus_vga: read back the cursor position bits of SR10/SR11" to start; I will send it to qemu-devel soon. vgasrc/clext.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/vgasrc/clext.c b/vgasrc/clext.c index 4d34bc44..11620856 100644 --- a/vgasrc/clext.c +++ b/vgasrc/clext.c @@ -21,7 +21,7 @@ ****************************************************************/ =20 /* VGA */ -static u16 cseq_vga[] VAR16 =3D {0x0007,0xffff}; +static u16 cseq_vga[] VAR16 =3D {0x0007,0x0012,0x0013,0xffff}; static u16 cgraph_vga[] VAR16 =3D {0x0009,0x000a,0x000b,0xffff}; static u16 ccrtc_vga[] VAR16 =3D {0x001a,0x001b,0x001d,0xffff}; =20 @@ -35,7 +35,7 @@ static u16 cgraph_svgacolor[] VAR16 =3D { static u16 cseq_640x480x8[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107, 0x580b,0x580c,0x580d,0x580e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x331b,0x331c,0x331d,0x331e, 0xffff }; @@ -51,7 +51,7 @@ static u16 ccrtc_640x480x8[] VAR16 =3D { static u16 cseq_640x480x16[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707, 0x580b,0x580c,0x580d,0x580e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x331b,0x331c,0x331d,0x331e, 0xffff }; @@ -67,7 +67,7 @@ static u16 ccrtc_640x480x16[] VAR16 =3D { static u16 cseq_640x480x24[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507, 0x580b,0x580c,0x580d,0x580e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x331b,0x331c,0x331d,0x331e, 0xffff }; @@ -83,7 +83,7 @@ static u16 ccrtc_640x480x24[] VAR16 =3D { static u16 cseq_800x600x8[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107, 0x230b,0x230c,0x230d,0x230e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x141b,0x141c,0x141d,0x141e, 0xffff }; @@ -98,7 +98,7 @@ static u16 ccrtc_800x600x8[] VAR16 =3D { static u16 cseq_800x600x16[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707, 0x230b,0x230c,0x230d,0x230e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x141b,0x141c,0x141d,0x141e, 0xffff }; @@ -113,7 +113,7 @@ static u16 ccrtc_800x600x16[] VAR16 =3D { static u16 cseq_800x600x24[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507, 0x230b,0x230c,0x230d,0x230e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x141b,0x141c,0x141d,0x141e, 0xffff }; @@ -128,7 +128,7 @@ static u16 ccrtc_800x600x24[] VAR16 =3D { static u16 cseq_1024x768x8[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107, 0x760b,0x760c,0x760d,0x760e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x341b,0x341c,0x341d,0x341e, 0xffff }; @@ -143,7 +143,7 @@ static u16 ccrtc_1024x768x8[] VAR16 =3D { static u16 cseq_1024x768x16[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707, 0x760b,0x760c,0x760d,0x760e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x341b,0x341c,0x341d,0x341e, 0xffff }; @@ -158,7 +158,7 @@ static u16 ccrtc_1024x768x16[] VAR16 =3D { static u16 cseq_1024x768x24[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507, 0x760b,0x760c,0x760d,0x760e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x341b,0x341c,0x341d,0x341e, 0xffff }; @@ -173,7 +173,7 @@ static u16 ccrtc_1024x768x24[] VAR16 =3D { static u16 cseq_1280x1024x8[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107, 0x760b,0x760c,0x760d,0x760e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x341b,0x341c,0x341d,0x341e, 0xffff }; @@ -188,7 +188,7 @@ static u16 ccrtc_1280x1024x8[] VAR16 =3D { static u16 cseq_1280x1024x16[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707, 0x760b,0x760c,0x760d,0x760e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x341b,0x341c,0x341d,0x341e, 0xffff }; @@ -204,7 +204,7 @@ static u16 ccrtc_1280x1024x16[] VAR16 =3D { static u16 cseq_1600x1200x8[] VAR16 =3D { 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107, 0x760b,0x760c,0x760d,0x760e, - 0x0412,0x0013,0x2017, + 0x0012,0x0013,0x2017, 0x341b,0x341c,0x341d,0x341e, 0xffff }; --=20 2.53.0 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org