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b=H4sIALUIL2gC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDUyMj3cSM5Exdi8RkM2NLS8skAwsTJaDSgqLUtMwKsDHRsbW1ALfb+6N WAAAA X-Change-ID: 20250522-ahci-8ac63999b084 To: seabios@seabios.org X-Developer-Signature: v=1; a=openpgp-sha256; l=2143; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=4bYxYJs95hzjHzaRRpN0Ps8wiFM9bpNA9lQ404sdfn4=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhgx9jv0RzMvSXZUUj8d7zlAJPd96MMe/Oz3GR154f06R0 9Sik3M6SlkYxLgYZMUUWUIElPo2NF5ccP1B1h+YOaxMIEMYuDgFYCIH+hgZ3ihLyS81iu6zFc97 b9Dzfk6Gzjr19rOvz3MssV3b5jzrDcM/PfnDLLwGnnWTejuXlDjsCj5vy7RC22jOjOygKS/W9NT wAQA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 X-Spam-Level: * X-MailFrom: jiaxun.yang@flygoat.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1 Message-ID-Hash: 7TIAQOPILIQKAPAMVQ3ALOL52EOEIXED X-Message-ID-Hash: 7TIAQOPILIQKAPAMVQ3ALOL52EOEIXED X-Mailman-Approved-At: Sat, 13 Sep 2025 21:08:14 +0000 CC: Jiaxun Yang X-Mailman-Version: 3.3.11b1 Precedence: list Subject: [SeaBIOS] [PATCH] ahci: Controller reset fixes List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: / X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZM-MESSAGEID: 1757797736367116600 Content-Type: text/plain; charset="utf-8" After adding AHCI controller functionality there are multiple reports on AHCI booting regression. As per my experiments on various machines, to reset controller properly it is necessary to poll HOST_CTL_RESET bit until it's clear. It is also required to read back HOST_CTL after changing HOST_CTL_AHCI_EN bits to ensure the controller has accepted write. Tested on ASMedia ASM1061, Intel H61 native SATA and AMD Phoenix native SATA. Link: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/= RDNRKWBN4N5XQX2TQMM5P4WZ2OOPPNAM/ Link: https://github.com/FlyGoat/csmwrap/issues/14 Fixes: 8863cbbd15a7 ("ahci: add controller reset") Signed-off-by: Jiaxun Yang --- To: seabios@seabios.org --- src/hw/ahci.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 2285d33d4ae21335e5222ab04608685b5bff3763..7e7a03ddd010d53fa439c8ca495= 05a2da00241f4 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -660,8 +660,23 @@ ahci_controller_setup(struct pci_device *pci) =20 pci_enable_busmaster(pci); =20 - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_RESET); - ahci_ctrl_writel(ctrl, HOST_CTL, HOST_CTL_AHCI_EN); + u32 val =3D ahci_ctrl_readl(ctrl, HOST_CTL); + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_RESET); + u32 end =3D timer_calc(AHCI_RESET_TIMEOUT); + for (;;) { + val =3D ahci_ctrl_readl(ctrl, HOST_CTL); + if (!(val & HOST_CTL_RESET)) + break; + if (timer_check(end)) { + warn_timeout(); + dprintf(1, "AHCI: controller reset failed\n"); + free(ctrl); + return; + } + yield(); + } + ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN); + (void)ahci_ctrl_readl(ctrl, HOST_CTL); /* Flush */ =20 ctrl->caps =3D ahci_ctrl_readl(ctrl, HOST_CAP); ctrl->ports =3D ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL); --- base-commit: 9029a010ec413e6c3c0eb52c29c252a5b9a9f774 change-id: 20250522-ahci-8ac63999b084 Best regards, --=20 Jiaxun Yang _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org