From nobody Fri Dec 19 17:11:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 1683270742920450.8869210261885; Fri, 5 May 2023 00:12:22 -0700 (PDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id 6FFA5220A3; Fri, 5 May 2023 07:12:19 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id 0F9AF22A61 for ; Fri, 5 May 2023 07:11:25 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-43-hqkWumDROCWII-tQW30O-Q-1; Fri, 05 May 2023 03:11:22 -0400 Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id E9393811E7C; Fri, 5 May 2023 07:11:21 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A8C46C15BA0; Fri, 5 May 2023 07:11:21 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) id C774618011EC; Fri, 5 May 2023 09:11:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1683270683; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Rlu4Dbr7nV6FubMH9YcoNGq9K+JqpiH6IUzURmGHJAM=; b=NgZf65zkF4N3yvH1HW42QRgULOhwlcuoecn+8xpK2PhxlzMIrUBYxUd+vrGv3dtyyVVF/r 30ufKuZgCmT9+nyYNXU/YwD0N4sarPVtbMYTIbXLNHEHfA2DIaedacwaBzQIL+eyHaGeKv 2pzXOKXO9RMEObky42QEPI2pyV5aD6o= X-MC-Unique: hqkWumDROCWII-tQW30O-Q-1 From: Gerd Hoffmann To: seabios@seabios.org Date: Fri, 5 May 2023 09:11:15 +0200 Message-Id: <20230505071117.369471-5-kraxel@redhat.com> In-Reply-To: <20230505071117.369471-1-kraxel@redhat.com> References: <20230505071117.369471-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 X-Spam-Level: ** Message-ID-Hash: EC5SBJNFVYGFPHUOS3QWN4YAG5B33Z63 X-Message-ID-Hash: EC5SBJNFVYGFPHUOS3QWN4YAG5B33Z63 X-MailFrom: kraxel@redhat.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: qemu-devel@nongnu.org, Gerd Hoffmann X-Mailman-Version: 3.3.6b1 Precedence: list Subject: [SeaBIOS] [PATCH v3 4/6] be less conservative with the 64bit pci io window List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: --- X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683270744563100001 Content-Type: text/plain; charset="utf-8" Current seabios code will only enable and use the 64bit pci io window in case it runs out of space in the 32bit pci mmio window below 4G. This patch will also enable the 64bit pci io window when (a) RAM above 4G is present, and (b) the physical address space size is known, and (c) seabios is running on a 64bit capable processor. This operates with the assumption that guests which are ok with memory above 4G most likely can handle mmio above 4G too. In case the 64bit pci io window is enabled also assign more memory to prefetchable pci bridge windows and the complete 64bit pci io window. The total mmio window size is 1/8 of the physical address space. Minimum bridge windows size is 1/256 of the total mmio window size. Signed-off-by: Gerd Hoffmann --- src/fw/pciinit.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 0fcd2be598a2..a6b5dff12bd3 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -51,6 +51,7 @@ u64 pcimem_end =3D BUILD_PCIMEM_END; u64 pcimem64_start =3D BUILD_PCIMEM64_START; u64 pcimem64_end =3D BUILD_PCIMEM64_END; u64 pci_io_low_end =3D 0xa000; +u32 pci_use_64bit =3D 0; =20 struct pci_region_entry { struct pci_device *dev; @@ -920,6 +921,8 @@ static int pci_bios_check_devices(struct pci_bus *busse= s) for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; + if (pci_use_64bit && (type =3D=3D PCI_REGION_TYPE_PREFMEM)) + align =3D (u64)1 << (CPUPhysBits - 11); if (!pci_bridge_has_region(s->bus_dev, type)) continue; u64 size =3D 0; @@ -1108,7 +1111,7 @@ static void pci_bios_map_devices(struct pci_bus *buss= es) panic("PCI: out of I/O address space\n"); =20 dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end); - if (pci_bios_init_root_regions_mem(busses)) { + if (pci_use_64bit || pci_bios_init_root_regions_mem(busses)) { struct pci_region r64_mem, r64_pref; r64_mem.list.first =3D NULL; r64_pref.list.first =3D NULL; @@ -1132,6 +1135,8 @@ static void pci_bios_map_devices(struct pci_bus *buss= es) u64 top =3D 1LL << CPUPhysBits; u64 size =3D (ALIGN(sum_mem, (1LL<<30)) + ALIGN(sum_pref, (1LL<<30))); + if (pci_use_64bit) + size =3D ALIGN(size, (1LL<<(CPUPhysBits-3))); if (r64_mem.base < top - size) { r64_mem.base =3D top - size; } @@ -1174,6 +1179,9 @@ pci_setup(void) =20 dprintf(3, "pci setup\n"); =20 + if (CPUPhysBits >=3D 36 && CPULongMode && RamSizeOver4G) + pci_use_64bit =3D 1; + dprintf(1, "=3D=3D=3D PCI bus & bridge init =3D=3D=3D\n"); if (pci_probe_host() !=3D 0) { return; --=20 2.40.1 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org