From nobody Wed Jan 15 09:38:13 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 16832707734469.886151489583654; Fri, 5 May 2023 00:12:53 -0700 (PDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id 9755827462; Fri, 5 May 2023 07:12:49 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id 4439B22F67 for ; Fri, 5 May 2023 07:11:25 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-349-jEEDYcpxNWutIkrtl8jEWw-1; Fri, 05 May 2023 03:11:21 -0400 Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9655E3806062; Fri, 5 May 2023 07:11:20 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5B12E492C13; Fri, 5 May 2023 07:11:20 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) id C066C1800986; Fri, 5 May 2023 09:11:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1683270684; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CXPCS+kJxlRKApXWmifHvPqleJ4x39uVxri/m9e/MXc=; b=SqrSHaX3mxY1qGv1Yiz5HTN2Hn4BNP1XtSDL7QwtjOjadrSKNY0rGciKd6BRK3F9Jskznf QndOdhbyYz0Ejx0GFPL2wrjEqUJO3wS2dBVLfmwyrSjN/17nI3Kl7EBBmKO6t6dLH/Xiqr Q7b4YFCg42uZUE5XgoyA6F9eL5J7aSI= X-MC-Unique: jEEDYcpxNWutIkrtl8jEWw-1 From: Gerd Hoffmann To: seabios@seabios.org Date: Fri, 5 May 2023 09:11:13 +0200 Message-Id: <20230505071117.369471-3-kraxel@redhat.com> In-Reply-To: <20230505071117.369471-1-kraxel@redhat.com> References: <20230505071117.369471-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 X-Spam-Level: ** Message-ID-Hash: J2FIKVRPQFWEMJEOX2SRIZBQWYVDZXCP X-Message-ID-Hash: J2FIKVRPQFWEMJEOX2SRIZBQWYVDZXCP X-MailFrom: kraxel@redhat.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: qemu-devel@nongnu.org, Gerd Hoffmann X-Mailman-Version: 3.3.6b1 Precedence: list Subject: [SeaBIOS] [PATCH v3 2/6] detect physical address space size List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: --- X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683270775249100001 Content-Type: text/plain; charset="utf-8" Check for pae and long mode using cpuid. If present also read the physical address bits. Apply some qemu sanity checks (see below). Record results in PhysBits and LongMode variables. In case we are not sure what the address space size is leave the PhysBits variable unset. On qemu we have the problem that for historical reasons x86_64 processors advertise 40 physical address space bits by default, even in case the host supports less than that so actually using the whole address space will not work. Because of that the code applies some extra sanity checks in case we find 40 (or less) physical address space bits advertised. Only known-good values (which is 40 for amd processors and 36+39 for intel processors) will be accepted as valid. Recommendation is to use 'qemu -cpu ${name},host-phys-bits=3Don' to advertise valid physical address space bits to the guest. Some distro builds enable this by default, and most likely the qemu default will change in near future too. Signed-off-by: Gerd Hoffmann --- src/fw/paravirt.h | 2 ++ src/fw/paravirt.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/src/fw/paravirt.h b/src/fw/paravirt.h index 4e2e993ba9d3..62a2cd075d2b 100644 --- a/src/fw/paravirt.h +++ b/src/fw/paravirt.h @@ -31,6 +31,8 @@ typedef struct QemuCfgDmaAccess { extern u32 RamSize; extern u64 RamSizeOver4G; extern int PlatformRunningOn; +extern u8 CPUPhysBits; +extern u8 CPULongMode; =20 static inline int runningOnQEMU(void) { return CONFIG_QEMU || ( diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index c880cb10a1bc..fc308bf1ef1d 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -32,6 +32,10 @@ u32 RamSize; // Amount of continuous ram >4Gig u64 RamSizeOver4G; +// physical address space bits +u8 CPUPhysBits; +// 64bit processor +u8 CPULongMode; // Type of emulator platform. int PlatformRunningOn VARFSEG; // cfg enabled @@ -129,6 +133,58 @@ static void kvmclock_init(void) tsctimer_setfreq(MHz * 1000, "kvmclock"); } =20 +static void physbits(int qemu_quirk) +{ + unsigned int max, eax, ebx, ecx, edx; + unsigned int physbits; + char signature[13]; + int pae =3D 0, valid =3D 0; + + cpuid(0, &eax, &ebx, &ecx, &edx); + memcpy(signature + 0, &ebx, 4); + memcpy(signature + 4, &edx, 4); + memcpy(signature + 8, &ecx, 4); + signature[12] =3D 0; + if (eax >=3D 1) { + cpuid(1, &eax, &ebx, &ecx, &edx); + pae =3D (edx & (1 << 6)); + } + + cpuid(0x80000000, &eax, &ebx, &ecx, &edx); + max =3D eax; + + if (max >=3D 0x80000001) { + cpuid(0x80000001, &eax, &ebx, &ecx, &edx); + CPULongMode =3D !!(edx & (1 << 29)); + } + + if (pae && CPULongMode && max >=3D 0x80000008) { + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + physbits =3D (u8)eax; + if (!qemu_quirk) { + valid =3D 1; + } else if (physbits >=3D 41) { + valid =3D 1; + } else if (strcmp(signature, "GenuineIntel") =3D=3D 0) { + if ((physbits =3D=3D 36) || (physbits =3D=3D 39)) + valid =3D 1; + } else if (strcmp(signature, "AuthenticAMD") =3D=3D 0) { + if (physbits =3D=3D 40) + valid =3D 1; + } + } else { + physbits =3D pae ? 36 : 32; + valid =3D 1; + } + + dprintf(1, "%s: signature=3D\"%s\", pae=3D%s, lm=3D%s, phys-bits=3D%d,= valid=3D%s\n", + __func__, signature, pae ? "yes" : "no", CPULongMode ? "yes" := "no", + physbits, valid ? "yes" : "no"); + + if (valid) + CPUPhysBits =3D physbits; +} + static void qemu_detect(void) { if (!CONFIG_QEMU_HARDWARE) @@ -161,6 +217,7 @@ static void qemu_detect(void) dprintf(1, "Running on QEMU (unknown nb: %04x:%04x)\n", v, d); break; } + physbits(1); } =20 static int qemu_early_e820(void); --=20 2.40.1 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org