From nobody Fri Mar 29 09:22:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 1650020662623832.6598085516715; Fri, 15 Apr 2022 04:04:22 -0700 (PDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id E680416E3D15; Fri, 15 Apr 2022 11:04:17 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id 7F99916E36E1 for ; Fri, 15 Apr 2022 11:03:59 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) for ; Fri, 15 Apr 2022 04:03:59 -0700 (PDT) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by smtp.gmail.com with ESMTPSA id w7-20020a63a747000000b003991d7d3728sm4329247pgo.74.2022.04.15.04.03.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 04:03:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GojuEpDkdZBo/YiOIHDsf7xs6WNeVLxlb978LSIc2cY=; b=G+RUcqVNpXzgY4q5blrx0Ty/gAHqKBS0bPu4QRjkW+/z6IBBiSspKtqZpvGBNTJQWj etqZLCOuOawT8YNn95i4O4jAGNIuQXy4wu6V9g1TJePS9WhhpPhk+m2O/PBMYrdZQyFO 761SlngqNKhta/IYEP+yEdifpj9drYjbCtil+Bzbe+9vIF3G3YuUx9yWAr55npMN1+gI LcIrZzcqfBCwt46nfx78G77+16qiy4nbuX9CPNCOETmIHfMrOcn7B/SCPpCy/UjK3aph EuqLxt/E/7woyiX5Zo6TwMloU+m0ydtqackWqyYeCw9dYDHgV5116PRW8jmL21YUn75H 3Wiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GojuEpDkdZBo/YiOIHDsf7xs6WNeVLxlb978LSIc2cY=; b=cWyK2T2ETLhb2umnXkM9YHVda8VerxvuUmWG2p+tPg8MbyeNs+Sy44EypNSyuJ8IPQ dEnU9WqeLv3g08BNcGoBIITJ36OYLWyxlnM9kG56axPIQJu5tqPBYQGi4fxJeikJ2LSN /s3aD/ly4qLuAPqUh9qKOIy7NzWQuvqZkil7HnBcVFdCPNozE/Zuai29RTtqIt1YOeUG QZ0lfN+ea65UfK0ChwbVFRS8+C5tEAl22elM5671vFdXTGYHyK/YvWYIGHBKWCk/rCnO BhNktBS4rh80akn8G7XtivjS5o3WNGXeZ+WuAGUlKwJrht81mu7ca+3WkBhR170wB/lE sJSw== X-Gm-Message-State: AOAM530BpaTLCd+4xlM31t7DUEVc5Gtnf6uASVG4t+tPdYOGaJpceKPU bKVkqVUvw8SLwT722oDwdpk= X-Google-Smtp-Source: ABdhPJyJcdfWXQFcIlEDtr5ol7KPEz3friP0BY16e/tpjUd0314do8mDm/1LXp4v4ifRA0eVLlBUPw== X-Received: by 2002:a63:6e43:0:b0:386:4801:13a6 with SMTP id j64-20020a636e43000000b00386480113a6mr5972359pgc.403.1650020637777; Fri, 15 Apr 2022 04:03:57 -0700 (PDT) From: Jay Khandkar To: seabios@seabios.org Date: Fri, 15 Apr 2022 16:33:34 +0530 Message-Id: <20220415110334.11996-1-jaykhandkar2002@gmail.com> MIME-Version: 1.0 X-Spam-Level: *** Message-ID-Hash: PE5R7BR52H7FOOEKWLYKMMMWV6JJEQJD X-Message-ID-Hash: PE5R7BR52H7FOOEKWLYKMMMWV6JJEQJD X-MailFrom: jaykhandkar2002@gmail.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: Jay Khandkar X-Mailman-Version: 3.3.5rc1 Precedence: list Subject: [SeaBIOS] [PATCH] MP: fix mptable interrupt source generation for pci devices List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: / X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650020663963100001 Content-Type: text/plain; charset="utf-8" Set the correct IOAPIC INTIN pin number for pci bus interrupt sources during MP spec table generation (on emulators). Currently, the pin number is set to the interrupt line field in the device's configuration space, which is set to either IRQ 10 or 11 as the boot rom driver expects. This works since qemu maps all ISA compatible PIC IRQs onto IOAPIC pins 0-15, including PIRQs. But it will break if, for some reason, the IRQ is routed to something other than the INTLINE value using, for eg. ACPI _CRS. This patch ensures the pin number is set to the correct value (16-23) that the INTx pin is routed to in APIC mode, in agreement with the ACPI _PRT provided routing. Tested on a Linux 5.17.2 guest on qemu with the pci=3Dnomsi and acpi=3Dnoirq boot parameters to force MP table parsing for interrupt sources. Signed-off-by: Jay Khandkar --- src/fw/mptable.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/src/fw/mptable.c b/src/fw/mptable.c index 47385cc..3a7b02f 100644 --- a/src/fw/mptable.c +++ b/src/fw/mptable.c @@ -18,6 +18,33 @@ #include "util.h" // MaxCountCPUs #include "x86.h" // cpuid =20 +/* table to obtain IOAPIC INTIN pin # for a certain pci slot and pin */ + +/* daisy chaining in line with acpi _PRT */ +#define SLOT_GSIE {0x14, 0x15, 0x16, 0x17} +#define SLOT_GSIF {0x15, 0x16, 0x17, 0x14} +#define SLOT_GSIG {0x16, 0x17, 0x14, 0x15} +#define SLOT_GSIH {0x17, 0x14, 0x15, 0x16} +#define SLOT_GSIA {0x10, 0x11, 0x12, 0x13} + +u8 pirq_intin[32][4] =3D { SLOT_GSIE, SLOT_GSIF, SLOT_GSIG, SLOT_GSIH, + SLOT_GSIE, SLOT_GSIF, SLOT_GSIG, SLOT_GSIH, + SLOT_GSIE, SLOT_GSIF, SLOT_GSIG, SLOT_GSIH, + SLOT_GSIE, SLOT_GSIF, SLOT_GSIG, SLOT_GSIH, + SLOT_GSIE, SLOT_GSIF, SLOT_GSIG, SLOT_GSIH, + SLOT_GSIE, SLOT_GSIF, SLOT_GSIG, SLOT_GSIH, + SLOT_GSIE, + + /* INTA -> PIRQA for slot 25 - 31, but 30 + see the default value of DIR */ + SLOT_GSIA, SLOT_GSIA, SLOT_GSIA, SLOT_GSIA, + SLOT_GSIA, + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + SLOT_GSIE, + + SLOT_GSIA }; + void mptable_setup(void) { @@ -114,7 +141,6 @@ mptable_setup(void) if (pci_bdf_to_bus(bdf) !=3D 0) break; int pin =3D pci_config_readb(bdf, PCI_INTERRUPT_PIN); - int irq =3D pci_config_readb(bdf, PCI_INTERRUPT_LINE); if (pin =3D=3D 0) continue; if (dev !=3D pci_bdf_to_busdev(bdf)) { @@ -131,7 +157,7 @@ mptable_setup(void) intsrc->srcbus =3D pci_bdf_to_bus(bdf); /* PCI bus */ intsrc->srcbusirq =3D (pci_bdf_to_dev(bdf) << 2) | (pin - 1); intsrc->dstapic =3D ioapic_id; - intsrc->dstirq =3D irq; + intsrc->dstirq =3D pirq_intin[pci_bdf_to_dev(bdf)][pin - 1]; intsrc++; } =20 --=20 2.35.2 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org