From nobody Thu Apr 25 16:58:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) client-ip=78.46.105.101; envelope-from=seabios-bounces@seabios.org; helo=coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of seabios.org designates 78.46.105.101 as permitted sender) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from coreboot.org (coreboot.org [78.46.105.101]) by mx.zohomail.com with SMTPS id 1637952420615144.28973588081874; Fri, 26 Nov 2021 10:47:00 -0800 (PST) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTPA id 256A116E3D5D; Fri, 26 Nov 2021 18:46:56 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by coreboot.org (Postfix) with ESMTP id C83DE16E3D2B for ; Fri, 26 Nov 2021 18:46:41 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) [209.132.183.4]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-562-Q6iRgNVwOJiO25u6jrGUlQ-1; Fri, 26 Nov 2021 13:46:38 -0500 Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1F9501006AA3 for ; Fri, 26 Nov 2021 18:46:38 +0000 (UTC) Received: from authenticated-user (PRIMARY_HOSTNAME [PUBLIC_IP]) by smtp.corp.redhat.com (Postfix) with ESMTP id CA09650D3F; Fri, 26 Nov 2021 18:46:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1637952400; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=jOzkYeV+OPd+W52zo8KeWNgHlUesaa5NN5Dotm+p5Ko=; b=Lb665GR6Pcht/diec4oY63PXNZyQBimAK+v2iYLB84sXDBnXRpQK8KCAy9hOdhBwyi85/8 e9jTqVDKE2Db+e0IZ0BK1PVCnPd/O2aihkB/kbfURPaM5D8g5QQMupzJlpjEDEGju2G8e2 Az/L0C9bP24DusSkjnvBKvukjakLpOM= X-MC-Unique: Q6iRgNVwOJiO25u6jrGUlQ-1 From: Igor Mammedov To: seabios@seabios.org Date: Fri, 26 Nov 2021 13:46:34 -0500 Message-Id: <20211126184634.167434-1-imammedo@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Message-ID-Hash: T5KKZMA3U64HW6OBUUL5VXBVWFYKWTKY X-Message-ID-Hash: T5KKZMA3U64HW6OBUUL5VXBVWFYKWTKY X-MailFrom: imammedo@redhat.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-seabios.seabios.org-0; header-match-seabios.seabios.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: mapfelba@redhat.com, kraxel@redhat.com, mst@redhat.com, lvivier@redhat.com, jusual@redhat.com X-Mailman-Version: 3.3.5rc1 Precedence: list Subject: [SeaBIOS] [PATCH] pci: reserve resources for pcie-pci-bridge to fix regressed hotplug on q35 with ACPI hotplug enabled List-Id: SeaBIOS mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Authentication-Results: coreboot.org; auth=pass smtp.auth=mailman@coreboot.org smtp.mailfrom=seabios-bounces@seabios.org X-Spamd-Bar: / X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1637952422687100001 hotplug of a PCI device to empty at startup pcie-pci-bridge fails when ACPI PCI hotplug (default since 6.1) is enabled due to lack of resources. Reproduced with: #QEMU-6.2-rc1 -machine q35 -device pcie-pci-bridge,id=3Dpcie-pci-bridge-0= ,addr=3D0x4 once linux guest is booted (test used Fedora 34), hotplug NIC from QEMU monitor: (qemu) device_add rtl8139,bus=3Dpcie-pci-bridge-0,addr=3D0x2 guest fails hotplug with: pci 0000:01:02.0: [10ec:8139] type 00 class 0x020000 pci 0000:01:02.0: reg 0x10: [io 0x0000-0x00ff] pci 0000:01:02.0: reg 0x14: [mem 0x00000000-0x000000ff] pci 0000:01:02.0: reg 0x30: [mem 0x00000000-0x0003ffff pref] pci 0000:01:02.0: BAR 6: no space for [mem size 0x00040000 pref] pci 0000:01:02.0: BAR 6: failed to assign [mem size 0x00040000 pref] pci 0000:01:02.0: BAR 0: no space for [io size 0x0100] pci 0000:01:02.0: BAR 0: failed to assign [io size 0x0100] pci 0000:01:02.0: BAR 1: no space for [mem size 0x00000100] pci 0000:01:02.0: BAR 1: failed to assign [mem size 0x00000100] 8139cp: 8139cp: 10/100 PCI Ethernet driver v1.3 (Mar 22, 2004) PCI Interrupt Link [GSIG] enabled at IRQ 22 8139cp 0000:01:02.0: no MMIO resource 8139cp: probe of 0000:01:02.0 failed with error -5 Reason for this is that commit [1] didn't take into account pcie-pci-bridge, marking bridge as non hotpluggable instead of handling it as possibly SHPC capable bridge. Fix issue by checking if pcie-pci-bridge is SHPC capable and if it is mark it as hotpluggable. With this hotplug of rtl8139 succeeds, with caveat that it fail initialize IO bar, which is caused by [2] which makes firmware skip IO reservation for any PCI device which isn't correct in case of pcie-pci-bridge. Fix it by exposing hotplug type and making resource optional only if PCIe hotplug is in use. Fixes regression in QEMU-6.1 and later, since it's switched to ACPI based PCI hotplug on Q35 by default at that time. RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=3D2001732 [1] Fixes: 3aa31d7d637 ("hw/pci: reserve IO and mem for pci express downstream = ports with no devices attached") [2] Fixes: 76327b9f32a ("fw/pci: do not automatically allocate IO region for PC= Ie bridges") Signed-off-by: Igor Mammedov CC: mapfelba@redhat.com CC: kraxel@redhat.com CC: mst@redhat.com CC: lvivier@redhat.com CC: jusual@redhat.com --- src/fw/pciinit.c | 49 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index d25931bb..3107a0e6 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -793,7 +793,13 @@ pci_region_create_entry(struct pci_bus *bus, struct pc= i_device *dev, return entry; } =20 -static int pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie_cap) +typedef enum hotplug_type_t { + HOTPLUG_NO_SUPPORTED =3D 0, + HOTPLUG_PCIE, + HOTPLUG_SHPC +} hotplug_type_t; + +static hotplug_type_t pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie= _cap) { u8 shpc_cap; =20 @@ -804,22 +810,31 @@ static int pci_bus_hotplug_support(struct pci_bus *bu= s, u8 pcie_cap) (__builtin_ffs(PCI_EXP_FLAGS_TYPE) - 1)); u8 downstream_port =3D (port_type =3D=3D PCI_EXP_TYPE_DOWNSTREAM) = || (port_type =3D=3D PCI_EXP_TYPE_ROOT_PORT); - /* - * PCI Express SPEC, 7.8.2: - * Slot Implemented =E2=80=93 When Set, this bit indicates that = the Link - * HwInit associated with this Port is connected to a slot (as - * compared to being connected to a system-integrated device or - * being disabled). - * This bit is valid for Downstream Ports. This bit is undefined - * for Upstream Ports. - */ - u16 slot_implemented =3D pcie_flags & PCI_EXP_FLAGS_SLOT; - - return downstream_port && slot_implemented; + + switch (port_type) { + case PCI_EXP_TYPE_PCI_BRIDGE: + /* fall-through to check if SHPC is enabled on bridge */ + break; + default: { + /* + * PCI Express SPEC, 7.8.2: + * Slot Implemented =E2=80=93 When Set, this bit indicat= es that the Link + * HwInit associated with this Port is connected to a sl= ot (as + * compared to being connected to a system-integrated de= vice or + * being disabled). + * This bit is valid for Downstream Ports. This bit is u= ndefined + * for Upstream Ports. + */ + u16 slot_implemented =3D pcie_flags & PCI_EXP_FLAGS_SLOT; + return downstream_port && slot_implemented ? + HOTPLUG_PCIE : HOTPLUG_NO_SUPPORTED; + break; + } + } } =20 shpc_cap =3D pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0= ); - return !!shpc_cap; + return !!shpc_cap ? HOTPLUG_SHPC : HOTPLUG_NO_SUPPORTED; } =20 /* Test whether bridge support forwarding of transactions @@ -904,7 +919,7 @@ static int pci_bios_check_devices(struct pci_bus *busse= s) u8 pcie_cap =3D pci_find_capability(bdf, PCI_CAP_ID_EXP, 0); u8 qemu_cap =3D pci_find_resource_reserve_capability(bdf); =20 - int hotplug_support =3D pci_bus_hotplug_support(s, pcie_cap); + hotplug_type_t hotplug_support =3D pci_bus_hotplug_support(s, pcie= _cap); for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; @@ -948,7 +963,9 @@ static int pci_bios_check_devices(struct pci_bus *busse= s) if (pci_region_align(&s->r[type]) > align) align =3D pci_region_align(&s->r[type]); u64 sum =3D pci_region_sum(&s->r[type]); - int resource_optional =3D pcie_cap && (type =3D=3D PCI_REGION_= TYPE_IO); + int resource_optional =3D 0; + if (hotplug_support =3D=3D HOTPLUG_PCIE) + resource_optional =3D pcie_cap && (type =3D=3D PCI_REGION_= TYPE_IO); if (!sum && hotplug_support && !resource_optional) sum =3D align; /* reserve min size for hot-plug */ if (size > sum) { --=20 2.27.0 _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org