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s=mta-01; t=1593195189; x= 1595009590; bh=VgxwOsTng8yXFF2TGZvkjGY1MYY+vfGNYc5dZxS9qxw=; b=B 4Qk6XEQMyspYiO/tCrgFDMf1iabFg84A20rMaE8sgt935jO+bZI9mmejsOtOY6De kNW1sMMdh1TkA1lwQOPar/T/qWCtYsyl4t5zLMhv/ghdklf+0w6w5DGB5h8rNJv8 ytZTaN2uKo9vNbVQaD1E7sefqL67OS8zngUNPPbnWM= X-Virus-Scanned: amavisd-new at yadro.com From: Roman Bolshakov To: Subject: [PATCH v2] timer: Handle decrements of PIT counter Date: Fri, 26 Jun 2020 21:06:58 +0300 Message-ID: <20200626180656.3441-1-r.bolshakov@yadro.com> X-Mailer: git-send-email 2.26.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.17.204.212] X-ClientProxiedBy: T-EXCH-01.corp.yadro.com (172.17.10.101) To T-EXCH-02.corp.yadro.com (172.17.10.102) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=89.207.88.252; envelope-from=r.bolshakov@yadro.com; helo=mta-01.yadro.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/26 14:13:11 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Roman Bolshakov , Kevin O'Connor , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @yadro.com) There's a fallback to PIT if TSC is not present but it doesn't work properly. It prevents boot from floppy on isapc and 486 cpu [1][2]. SeaBIOS configures PIT in Mode 2. PIT counter is decremented in the mode but timer_adjust_bits() thinks that the counter overflows and increases 32-bit tick counter on each detected "overflow". Invalid overflow detection results in 55ms time advance (1 / 18.2Hz) on each read from PIT counter. So all timers expire much faster and 5-second floppy timeout expires in 83 real microseconds (or just a bit longer). It can be fixed by making the counter recieved from PIT an increasing value so it can be passed to timer_adjust_bits(): 0, 1, 2 and up to 65535 and then the counter is re-loaded with 0. 1. https://bugs.launchpad.net/seabios/+bug/1840719 2. https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg03924.html Fixes: eac11944019 ("Unify pmtimer_read() and pittimer_read() code.") Reported-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Roman Bolshakov --- Changes since v1: - Simplified change of counter direction (Kevin) src/hw/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hw/timer.c b/src/hw/timer.c index 56bb289..b6f102e 100644 --- a/src/hw/timer.c +++ b/src/hw/timer.c @@ -180,7 +180,7 @@ timer_read(void) // Read from PIT. outb(PM_SEL_READBACK | PM_READ_VALUE | PM_READ_COUNTER0, PORT_PIT_MODE= ); u16 v =3D inb(PORT_PIT_COUNTER0) | (inb(PORT_PIT_COUNTER0) << 8); - return timer_adjust_bits(v, 0xffff); + return timer_adjust_bits(-v, 0xffff); } =20 // Return the TSC value that is 'msecs' time in the future. --=20 2.26.1