From nobody Thu Apr 25 20:12:52 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1541420905268204.91120449552693; Mon, 5 Nov 2018 04:28:25 -0800 (PST) Received: from [127.0.0.1] (helo=ra.coreboot.org) by mail.coreboot.org with esmtp (Exim 4.88) (envelope-from ) id 1gJdyY-0008P9-WF; Mon, 05 Nov 2018 13:27:27 +0100 Received: from 2.mo6.mail-out.ovh.net ([46.105.76.65]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.88) (envelope-from ) id 1gJdyK-0008OZ-5H for seabios@seabios.org; Mon, 05 Nov 2018 13:27:24 +0100 Received: from player687.ha.ovh.net (unknown [10.109.146.211]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id A9A1E19613D for ; Mon, 5 Nov 2018 13:27:15 +0100 (CET) Received: from 3mdeb.com (109241231046.gdansk.vectranet.pl [109.241.231.46]) (Authenticated sender: krystian.hebel@3mdeb.com) by player687.ha.ovh.net (Postfix) with ESMTPSA id 16FD42C00D5; Mon, 5 Nov 2018 13:27:13 +0100 (CET) From: Krystian Hebel To: seabios@seabios.org Date: Mon, 5 Nov 2018 13:27:10 +0100 Message-Id: <20181105122710.19319-1-krystian.hebel@3mdeb.com> X-Mailer: git-send-email 2.17.1 X-Ovh-Tracer-Id: 3973019299930626882 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: 0 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrjeehgdegudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecu X-Spam-Score: -2.5 (--) Subject: [SeaBIOS] [PATCH] coreboot: update memory table before handling execution to payload/system X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff Content-Type: text/plain; charset="utf-8" SeaBIOS modifies its internal e820 structure, but does not propagate these changes back to coreboot tables. This resulted in multiple errors in MemTest86 when run on 2 GB platforms, probably because of some memory-mapped devices. This patch copies back modified e820 tables before booting an OS or a payload. Change-Id: I16a3f059695717daedb1e997ce4e62018c7e02b3 Signed-off-by: Krystian Hebel --- src/e820map.c | 2 ++ src/e820map.h | 2 ++ src/fw/coreboot.c | 50 +++++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 50 insertions(+), 4 deletions(-) diff --git a/src/e820map.c b/src/e820map.c index 39445cf6399d..2d2de6094b14 100644 --- a/src/e820map.c +++ b/src/e820map.c @@ -148,5 +148,7 @@ e820_remove(u64 start, u64 size) void e820_prepboot(void) { + // Synchronize memory maps. + coreboot_update_memtable(); dump_map(); } diff --git a/src/e820map.h b/src/e820map.h index de8b523003c5..78bf1ce76572 100644 --- a/src/e820map.h +++ b/src/e820map.h @@ -23,4 +23,6 @@ void e820_prepboot(void); extern struct e820entry e820_list[]; extern int e820_count; =20 +extern void coreboot_update_memtable(void); + #endif // e820map.h diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c index 7c0954b5398c..aa07baad3a7f 100644 --- a/src/fw/coreboot.c +++ b/src/fw/coreboot.c @@ -189,10 +189,6 @@ coreboot_preinit(void) e820_add(m->start, m->size, type); } =20 - // Ughh - coreboot likes to set a map at 0x0000-0x1000, but this - // confuses grub. So, override it. - e820_add(0, 16*1024, E820_RAM); - struct cb_cbmem_ref *cbref =3D find_cb_subtable(cbh, CB_TAG_CBMEM_CONS= OLE); if (cbref) { cbcon =3D (void*)(u32)cbref->cbmem_addr; @@ -567,3 +563,49 @@ cbfs_payload_setup(void) boot_add_cbfs(cfile->fhdr, desc, bootprio_find_named_rom(filename,= 0)); } } + +// Mirror changes done on e820 to coreboot tables. +void +coreboot_update_memtable(void) +{ + if (!CONFIG_COREBOOT) + return; + + // Find coreboot table. + struct cb_header *cbh =3D find_cb_table(); + if (!cbh) { + dprintf(1, "Unable to find coreboot table!\n"); + return; + } + char *end =3D (char *)cbh + sizeof(*cbh) + cbh->table_bytes; + dprintf(3, "Now attempting to find coreboot memory map\n"); + struct cb_memory *dst =3D find_cb_subtable(cbh, CB_TAG_MEMORY); + if (!dst) { + dprintf(1, "Unable to find coreboot memory table!\n"); + return; + } + + // Remove old memory table, overwriting it with following subtables + // and append an updated memory table to the end. + u32 old_size =3D dst->size; + char *src =3D (char *)dst + old_size; + memcpy(dst, src, (end - src)); + dst =3D (struct cb_memory *)(end - old_size); + u32 new_size =3D e820_count * sizeof(struct e820entry); + dst->tag =3D CB_TAG_MEMORY; + // Tables are binary compatible, except that CB_MEM_TABLE became + // E820_RESERVED. + memcpy((char*)dst + sizeof(struct cb_memory), e820_list, new_size); + new_size +=3D sizeof(struct cb_memory); + dst->size =3D new_size; + + // Update header fields (size and checksum). + cbh->table_bytes +=3D new_size - old_size; + cbh->table_checksum =3D ipchksum((char*)cbh + sizeof(*cbh), cbh->table= _bytes); + cbh->header_checksum =3D 0; + cbh->header_checksum =3D ipchksum((char*)cbh, sizeof(*cbh)); + + // Ughh - coreboot likes to set a map at 0x0000-0x1000, but this + // confuses grub. So, override it in e820 only. + e820_add(0, 16*1024, E820_RAM); +} --=20 2.17.1 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios