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[45.78.72.26]) by smtp.gmail.com with ESMTPSA id b14-v6sm28183893pfc.178.2018.09.17.08.03.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Sep 2018 08:03:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Buq9OHIdqvhiKdo/Jb5TrTULBG96HxM01n1V/W6AQ3s=; b=C89Ohkyi2Mp+LyXBRLGxY2JbNNN3lzw8O9nOW6/BLkTGSnRxdnaYYDQvrWzJrBEL9/ 1ibEGxbVM8odAFYlpCM5KnolRgQXMt7Ql8fEog6fjV+u+nhvgJGAtUsGkzjn8CqkFkT7 3WBBJMkG6OkzJ8VKTH/nuNb6vFu4duMVcGiCeQymNCmMdODUN0nvWCF9GGe16h1FwQ+E xaDpeFLourtgf4wlztpiM4A+fE/lsfqNfIMrd6i6IDCYlxW9mx3cWTXvY1KzrWxyr9Xv 7jHGRpGJ9vrfTH7Q2M1gkorckmSFztN+xZZw62yt7q/Cq5gJPHlb1LJ61Rab/Bd5LNa1 PskA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Buq9OHIdqvhiKdo/Jb5TrTULBG96HxM01n1V/W6AQ3s=; b=gjbBv+SpVRdd8iI5TzSN0qh+JLzXC6TOsVKJ4BklhiptzwvDx9zLd6Bt38SArJKDTw 1hzuRpcMg/AvIaEw1RJ0tDNEsO9xL+P5qtvPD3+iIDyQ2pPiCMzpwa7QRO83nK7tO599 2xa362e9YmNdjhjb0HZK+6QUHohdLnB79XYeLOGIn0KaEvRJ9tQ3v8UNaf8Olizp7LxK GheJq+qqhSUJb03MehcPdsK4ahPH7jwa9ra0Sc0ZVSJU6lCDn4y8tZTvvAffukS6854v /AULiOg2QK0Ezf5zBrvogJVdELpeCB1n4xxQyYrdKwY830CkLNL7KCES9c46QlVqQktV 4IBA== X-Gm-Message-State: APzg51AX16pXuhJzci1DYWOu/2avJsSxPqekjUYW1F/YMoD2ktaEjtC4 LmWrFtC6P8QT8Fai/u52pp4DER9cScY= X-Google-Smtp-Source: ANB0VdZcFTRdkCYE9foV3bYgTlkecaHQFWgYBQFtBeLYljOkj5E9dRbh6ekmOLR9T40Txso35vYZqw== X-Received: by 2002:a62:d544:: with SMTP id d65-v6mr26345286pfg.107.1537196597906; Mon, 17 Sep 2018 08:03:17 -0700 (PDT) From: Zihan Yang To: seabios@seabios.org Date: Mon, 17 Sep 2018 23:02:59 +0800 Message-Id: <1537196579-12825-2-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537196579-12825-1-git-send-email-whois.zihan.yang@gmail.com> References: <1537196579-12825-1-git-send-email-whois.zihan.yang@gmail.com> X-Spam-Score: -5.8 (-----) Subject: [SeaBIOS] [RFC v3] pciinit: setup mcfg for pxb-pcie to support multiple pci domains X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" To support multiple pci domains of pxb-pcie device in qemu, we need to setup mcfg range in seabios. We use [0x80000000, 0xb0000000) to hold new domain m= cfg table for now, and we need to retrieve the desired mcfg size of each pxb-pc= ie from a hidden bar because they may not need the whole 256 busses, which also enables us to support more domains within a limited range (768MB) Signed-off-by: Zihan Yang --- src/fw/dev-q35.h | 7 +++++++ src/fw/pciinit.c | 32 ++++++++++++++++++++++++++++++++ src/hw/pci_ids.h | 1 + 3 files changed, 40 insertions(+) diff --git a/src/fw/dev-q35.h b/src/fw/dev-q35.h index 201825d..229cd81 100644 --- a/src/fw/dev-q35.h +++ b/src/fw/dev-q35.h @@ -49,4 +49,11 @@ #define ICH9_APM_ACPI_ENABLE 0x2 #define ICH9_APM_ACPI_DISABLE 0x3 =20 +#define PXB_PCIE_HOST_BRIDGE_MCFG_BAR 0x50 /* 64bit regist= er */ +#define PXB_PCIE_HOST_BRIDGE_MCFG_SIZE 0x58 /* 32bit regist= er */ +#define PXB_PCIE_HOST_BRIDGE_ENABLE Q35_HOST_BRIDGE_PCIEXBA= REN +/* pxb-pcie can use [0x80000000, 0xb0000000), be careful not to overflow */ +#define PXB_PCIE_HOST_BRIDGE_MCFG_SIZE_ADDR 0x80000000 +#define PXB_PCIE_HOST_BRIDGE_MCFG_SIZE_ADDR_UPPER Q35_HOST_BRIDGE_PCIEXBAR= _ADDR + #endif // dev-q35.h diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index c0634bc..e0ac22c 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -51,6 +51,7 @@ u64 pcimem_end =3D BUILD_PCIMEM_END; u64 pcimem64_start =3D BUILD_PCIMEM64_START; u64 pcimem64_end =3D BUILD_PCIMEM64_END; u64 pci_io_low_end =3D 0xa000; +u64 pxb_pcie_mcfg_base =3D PXB_PCIE_HOST_BRIDGE_MCFG_SIZE_ADDR; =20 struct pci_region_entry { struct pci_device *dev; @@ -507,11 +508,42 @@ static void mch_mem_addr_setup(struct pci_device *dev= , void *arg) pci_io_low_end =3D acpi_pm_base; } =20 +static void pxb_pcie_mem_addr_setup(struct pci_device *dev, void *arg) +{ + u64 mcfg_base; + u32 mcfg_size =3D pci_config_readl(dev->bdf, PXB_PCIE_HOST_BRIDGE_MCFG= _SIZE); + + /* 0 means this pxb-pcie still resides in pci domain 0 */ + if (mcfg_size =3D=3D 0) + return; + + if (pxb_pcie_mcfg_base + mcfg_size > + PXB_PCIE_HOST_BRIDGE_MCFG_SIZE_ADDR_UPPER) { + dprintf(1, "PCI: Not enough space to hold new pci domains\n"); + return; + } + + mcfg_base =3D pxb_pcie_mcfg_base; + pxb_pcie_mcfg_base +=3D mcfg_size; + + /* First clear old mmio, taken care of by QEMU */ + pci_config_writel(dev->bdf, PXB_PCIE_HOST_BRIDGE_MCFG_BAR, 0); + /* Update MCFG base */ + pci_config_writel(dev->bdf, PXB_PCIE_HOST_BRIDGE_MCFG_BAR + 4, + mcfg_base >> 32); + pci_config_writel(dev->bdf, PXB_PCIE_HOST_BRIDGE_MCFG_BAR, + (mcfg_base & 0xffffffff) | PXB_PCIE_HOST_BRIDGE_ENAB= LE); + + e820_add(mcfg_base, mcfg_size, E820_RESERVED); +} + static const struct pci_device_id pci_platform_tbl[] =3D { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, i440fx_mem_addr_setup), PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH, mch_mem_addr_setup), + PCI_DEVICE(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_PXB_HOST, + pxb_pcie_mem_addr_setup), PCI_DEVICE_END }; =20 diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 1096461..b495920 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2266,6 +2266,7 @@ #define PCI_VENDOR_ID_REDHAT 0x1b36 #define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 +#define PCI_DEVICE_ID_REDHAT_PXB_HOST 0x000B =20 #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios