From nobody Wed May 1 19:38:54 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501964906048391.71401306036114; Sat, 5 Aug 2017 13:28:26 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1de5do-0004DM-Ma; Sat, 05 Aug 2017 22:25:44 +0200 Received: from mail-lf0-f65.google.com ([209.85.215.65]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1de5dd-0004Au-2A for seabios@seabios.org; Sat, 05 Aug 2017 22:25:42 +0200 Received: by mail-lf0-f65.google.com with SMTP id y15so3061059lfd.5 for ; Sat, 05 Aug 2017 13:27:55 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id e42sm1978197lji.81.2017.08.05.13.27.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:27:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3ZfGBL3FcTmLBBVcx+/pYcBbEuP08DHyTy4y02qSYIY=; b=AE7+h1Ab45ISwiWqgBo+GezZSs2AIlkgBg9xjuokBO+yP5JPU8B/K/e2enr9ih4+iK j97QLpSh6B7lWL83ZJN5ww0eLwyKn5Ru30PvXQNF8rirxCu/VvnquQMhZHS6VMJu47c6 UGWUkMSmYaAhPAFPrF5NsiDhDkGs6Kgpf2OyhS/WySyfdnfuzZAJWca3QRgS1+6rlzeb j1XAGCzXVEyxbHTRwfR8UoroVFdt3xjoCE0QqsGzAU0JO3LwcqZCBkZ1ITSjbpMPScen Q7PribwrRn9JL4fVruwPX10rH1LXiY1ZLN5hcOB5P8ZfCi/NgzXoA2OwOGZbsvxsoELa 7lpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3ZfGBL3FcTmLBBVcx+/pYcBbEuP08DHyTy4y02qSYIY=; b=TO1WCFOwy/Eak5E434ZNFemUfFXsXNY2+Ybn7+ssBEPJ7+7ThGeapdXPRl1+bXOgwZ 1ysMGQ65FgwWlaHBfalKFqQUQ0Uky7N9IWa7qM3jfQ7QvsoPdesTum/DXjRKqVikPP/H I+27kGLrS5UORyLkitK79/sXkFdmRpSOygRLPw9P3Yr6AUjlFxyp1LPh0H8p9BBlfdNY RDfVojfEfu7rKowmBHOcmMVSysxnh3+4kHXAtGFJ9x+nKlGIrP3lr2AvyvzyXCpTV1iM lwobskVRHv3S9g2R5NU5uoxOLkuIZlVknlVxPXsbr01PeJ5xVg/KDYatnhKoGWYpAjnD LCMw== X-Gm-Message-State: AHYfb5j7ytOF6p8eSlzQjY66sR/Wm74lfavdsYguzAi4UJNsOAUVhINZ D5mpDwInFWPRJw== X-Received: by 10.25.212.136 with SMTP id l130mr2024196lfg.189.1501964874177; Sat, 05 Aug 2017 13:27:54 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 5 Aug 2017 23:27:34 +0300 Message-Id: <1501964858-5159-2-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> References: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.1 (--) Subject: [SeaBIOS] [PATCH v4 1/5] hw/i386: allow SHPC for Q35 machine X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Unmask previously masked SHPC feature in _OSC method. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/i386/acpi-build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index b9c245c..98dd424 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1862,9 +1862,9 @@ static Aml *build_q35_osc_method(void) =20 /* * Always allow native PME, AER (no dependencies) - * Never allow SHPC (no SHPC controller in this system) + * Allow SHPC (PCI bridges can have SHPC controller) */ - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); + aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); =20 if_ctx2 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); /* Unknown revision */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Wed May 1 19:38:54 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501964909159595.1997660787913; Sat, 5 Aug 2017 13:28:29 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1de5dx-0004Hs-3L; Sat, 05 Aug 2017 22:25:53 +0200 Received: from mail-lf0-f66.google.com ([209.85.215.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1de5de-0004BO-MQ for seabios@seabios.org; Sat, 05 Aug 2017 22:25:50 +0200 Received: by mail-lf0-f66.google.com with SMTP id x16so3070654lfb.4 for ; Sat, 05 Aug 2017 13:27:57 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id e42sm1978197lji.81.2017.08.05.13.27.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:27:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+MU7tdbvDvnB7a07Vnr/ZJrx1PSRWgMdXKiFQT0wcws=; b=evR0xrUdLDSWm7dGwQHa1xygLfO0iAe5zbHUEkGoXb83Zimc2L/208cwA/PzNOIO0R 4gWNL+lJiNEQvQ4B2XuZMl/T8XV0wN6CVkzVBybM9sfjdKCazcYH4cmqHq80L9luIiB4 JuX9Ye6tgAOVEFTMnlKtBqcVDoD8Fsor5dWsmNuX2dxYf5GZI/ST8QtsisDQ9PVSuH3h nKzq8dfMCbXtluQAlKbKsaaeUJwumB6nVEc4qlo+/hg8JRT0kEaMEaaVHWC2pvzvtKAb vFN7OXmBtHKPzsCf6qQMCXC2K0YypIDkxeGWGu7j/ga44N9t3GRoAUIhge3NY0/MIYqi aX/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+MU7tdbvDvnB7a07Vnr/ZJrx1PSRWgMdXKiFQT0wcws=; b=fZgvmrzUVjA3ZKH1M4Ecatu6KatRqy1cd9h1JSzoK1sM8Ceq9huilhy6eC2741VGwZ Zc/g+Wlmlzs105VtK2U57iM2FJe7IYjYU+7nU9w9JMOnzjJEbBKRxr9uuA00Cmwah+dU fDtY1xO2hl5sTUh/hZVdZkXR9ib/7FWlLtucuB03MM8YnAeq59KZdDu6Cz2bmPXzsKLi XHJ+R6yCY0YQ7MK0jiUbtr+vTlaARqzl/x+Eph8Yu/9l4I/xCezRhEP5WVNyhy2LyHzG XUkH6lhsZkCGiRgxuJOwY5ociEowaXE8EjlYINZlcg9OnKqS3QuwJW01OHdiMSDY9rtw ZxOQ== X-Gm-Message-State: AIVw112s7xAWAUhYTZBq4iV2EFhMFjeQY05XLmohvGVdhwv5BDZgTpTr Gb5ydit24QmWdw== X-Received: by 10.46.1.201 with SMTP id f70mr1905432lji.182.1501964875726; Sat, 05 Aug 2017 13:27:55 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 5 Aug 2017 23:27:35 +0300 Message-Id: <1501964858-5159-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> References: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -5.4 (-----) Subject: [SeaBIOS] [PATCH v4 2/5] hw/pci: introduce pcie-pci-bridge device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce a new PCIExpress-to-PCI Bridge device, which is a hot-pluggable PCI Express device and supports devices hot-plug with SHPC. This device is intended to replace the DMI-to-PCI Bridge in an overwhelming majority of use-cases. Signed-off-by: Aleksandr Bezzubikov --- hw/pci-bridge/Makefile.objs | 2 +- hw/pci-bridge/pcie_pci_bridge.c | 212 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci/pci.h | 1 + 3 files changed, 214 insertions(+), 1 deletion(-) create mode 100644 hw/pci-bridge/pcie_pci_bridge.c diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs index c4683cf..666db37 100644 --- a/hw/pci-bridge/Makefile.objs +++ b/hw/pci-bridge/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-y +=3D pci_bridge_dev.o +common-obj-y +=3D pci_bridge_dev.o pcie_pci_bridge.o common-obj-$(CONFIG_PCIE_PORT) +=3D pcie_root_port.o gen_pcie_root_port.o common-obj-$(CONFIG_PXB) +=3D pci_expander_bridge.o common-obj-$(CONFIG_XIO3130) +=3D xio3130_upstream.o xio3130_downstream.o diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c new file mode 100644 index 0000000..4127725 --- /dev/null +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -0,0 +1,212 @@ +/* + * QEMU Generic PCIE-PCI Bridge + * + * Copyright (c) 2017 Aleksandr Bezzubikov + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/msi.h" +#include "hw/pci/shpc.h" +#include "hw/pci/slotid_cap.h" + +typedef struct PCIEPCIBridge { + /*< private >*/ + PCIBridge parent_obj; + + OnOffAuto msi; + MemoryRegion shpc_bar; + /*< public >*/ +} PCIEPCIBridge; + +#define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge" +#define PCIE_PCI_BRIDGE_DEV(obj) \ + OBJECT_CHECK(PCIEPCIBridge, (obj), TYPE_PCIE_PCI_BRIDGE_DEV) + +static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) +{ + PCIBridge *br =3D PCI_BRIDGE(d); + PCIEPCIBridge *pcie_br =3D PCIE_PCI_BRIDGE_DEV(d); + int rc, pos; + + pci_bridge_initfn(d, TYPE_PCI_BUS); + + d->config[PCI_INTERRUPT_PIN] =3D 0x1; + memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar", + shpc_bar_size(d)); + rc =3D shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp); + if (rc) { + goto error; + } + + rc =3D pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp); + if (rc < 0) { + goto cap_error; + } + + pos =3D pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); + if (pos < 0) { + goto pm_error; + } + d->exp.pm_cap =3D pos; + pci_set_word(d->config + pos + PCI_PM_PMC, 0x3); + + pcie_cap_arifwd_init(d); + pcie_cap_deverr_init(d); + + rc =3D pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, errp); + if (rc < 0) { + goto aer_error; + } + + if (pcie_br->msi !=3D ON_OFF_AUTO_OFF) { + rc =3D msi_init(d, 0, 1, true, true, errp); + if (rc < 0) { + goto msi_error; + } + } + pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &pcie_br->shpc_bar); + return; + +msi_error: + pcie_aer_exit(d); +aer_error: +pm_error: + pcie_cap_exit(d); +cap_error: + shpc_free(d); +error: + pci_bridge_exitfn(d); +} + +static void pcie_pci_bridge_exit(PCIDevice *d) +{ + PCIEPCIBridge *bridge_dev =3D PCIE_PCI_BRIDGE_DEV(d); + pcie_cap_exit(d); + shpc_cleanup(d, &bridge_dev->shpc_bar); + pci_bridge_exitfn(d); +} + +static void pcie_pci_bridge_reset(DeviceState *qdev) +{ + PCIDevice *d =3D PCI_DEVICE(qdev); + pci_bridge_reset(qdev); + msi_reset(d); + shpc_reset(d); +} + +static void pcie_pci_bridge_write_config(PCIDevice *d, + uint32_t address, uint32_t val, int len) +{ + pci_bridge_write_config(d, address, val, len); + msi_write_config(d, address, val, len); + shpc_cap_write_config(d, address, val, len); +} + +static Property pcie_pci_bridge_dev_properties[] =3D { + DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_ON), + DEFINE_PROP_END_OF_LIST(), +}; + +static bool pcie_pci_bridge_shpc_present(void *opaque, int version_id) +{ + return true; +} + +static const VMStateDescription pcie_pci_bridge_dev_vmstate =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), + SHPC_VMSTATE(shpc, PCIDevice, pcie_pci_bridge_shpc_present), + VMSTATE_END_OF_LIST() + } +}; + +static void pcie_pci_bridge_hotplug_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hotplug_cb(hotplug_dev, dev, errp); +} + +static void pcie_pci_bridge_hot_unplug_request_cb(HotplugHandler *hotplug_= dev, + DeviceState *dev, + Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hot_unplug_request_cb(hotplug_dev, dev, errp); +} + +static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); + + k->is_express =3D 1; + k->is_bridge =3D 1; + k->vendor_id =3D PCI_VENDOR_ID_REDHAT; + k->device_id =3D PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE; + k->realize =3D pcie_pci_bridge_realize; + k->exit =3D pcie_pci_bridge_exit; + k->config_write =3D pcie_pci_bridge_write_config; + dc->vmsd =3D &pcie_pci_bridge_dev_vmstate; + dc->props =3D pcie_pci_bridge_dev_properties; + dc->vmsd =3D &pcie_pci_bridge_dev_vmstate; + dc->reset =3D &pcie_pci_bridge_reset; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + hc->plug =3D pcie_pci_bridge_hotplug_cb; + hc->unplug_request =3D pcie_pci_bridge_hot_unplug_request_cb; +} + +static const TypeInfo pcie_pci_bridge_info =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .parent =3D TYPE_PCI_BRIDGE, + .instance_size =3D sizeof(PCIEPCIBridge), + .class_init =3D pcie_pci_bridge_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { }, + } +}; + +static void pciepci_register(void) +{ + type_register_static(&pcie_pci_bridge_info); +} + +type_init(pciepci_register); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e598b09..b33a34f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -98,6 +98,7 @@ #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d +#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 =20 #define FMT_PCIBUS PRIx64 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Wed May 1 19:38:54 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501964911148347.14979282523507; Sat, 5 Aug 2017 13:28:31 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1de5du-0004G7-4n; Sat, 05 Aug 2017 22:25:50 +0200 Received: from mail-lf0-f66.google.com ([209.85.215.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1de5dh-0004Bg-HI for seabios@seabios.org; Sat, 05 Aug 2017 22:25:49 +0200 Received: by mail-lf0-f66.google.com with SMTP id x16so3070686lfb.4 for ; Sat, 05 Aug 2017 13:28:00 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id e42sm1978197lji.81.2017.08.05.13.27.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:27:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PL8+xV0F7+Aeqbl11BcoYp+Li+2ISLsndy0/X6SE358=; b=i8HYhbpcbKkU2tszZC1gkPCPJTkzHWLq5LyhSyZLWcO9ABrfZfzfJpm8cNszXk+pmd PJ8G5EZ9K/1I4uZ9gj9HdWOcH/ZF48ag96ngH5BeBE7Xo+rL0dlthBr3BGmwQNd0fD5H nO9WBShu6ptlK6JiH/+koHrldFHq1eGd16PR8ZoQcyPZrShFSxymUE3TqFUvnjjzA2om TJkq1JSZQX1AytgDS+ofPD0SS5LmMR/t7v0aYmZxX1QPoZvEQWKBc6KfpBYpqrHfxa3Y Bk6bGFw80jNB5iJ/ApKNCoXlC83kij3ZQQ3xz3b34yKYf0VWHNeqrU+HztpC5O1PsQXc 1rdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PL8+xV0F7+Aeqbl11BcoYp+Li+2ISLsndy0/X6SE358=; b=hZU6FcguqYbiVKrJev8B5IHt7yxNrfcXQzzwyMb+5lizwtrhqxo9M/45Ct43BTpXgd hN/cVXPx9ZX1cN4iDk/w2oWCLbVwD7NxeefT7lOXa9chR7TogtoWWp22idPrDbkBmvM3 bHHJJeuRjeR89Wy7WUbk7gIMAdg4QeAyFq7RSc4GBdmJcGmacoMo9OHkhGzy8wLzP6uD uXpaapI2/HYFi4XfrCL/Lf9bDYyAeX6LowaG6AhEpbdPeDqgPKmLj5wwSSAu3bddasx2 tBaSR/hfyp+yxQO+vORJoVZ73Vx52D09d5Wvo2Rm85x9i0cOKurTCFDzcTO4KgHy2dZ6 XlqA== X-Gm-Message-State: AHYfb5h/vP95ByHMi11uQ1hJHGN+8tjtbD9hKD1FiwmtizUB2k6UmUAa JA5v8tRTejz2dpsf8Ss= X-Received: by 10.46.77.77 with SMTP id a74mr2184986ljb.53.1501964878633; Sat, 05 Aug 2017 13:27:58 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 5 Aug 2017 23:27:36 +0300 Message-Id: <1501964858-5159-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> References: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.6 (--) Subject: [SeaBIOS] [PATCH v4 3/5] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridges may need some extra info about bus number, IO, memory and prefetchable memory to reserve. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov --- hw/pci/pci_bridge.c | 29 +++++++++++++++++++++++++++++ include/hw/pci/pci_bridge.h | 21 +++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 720119b..889950d 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -408,6 +408,35 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus= _name, br->bus_name =3D bus_name; } =20 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_reserve, + uint64_t non_pref_mem_reserve, + uint64_t pref_mem_reserve, + Error **errp) +{ + size_t cap_len =3D sizeof(PCIBridgeQemuCap); + PCIBridgeQemuCap cap =3D { + .len =3D cap_len, + .type =3D REDHAT_PCI_CAP_QEMU_RESERVE, + .bus_res =3D bus_reserve, + .io =3D io_reserve, + .mem =3D non_pref_mem_reserve, + .mem_pref =3D pref_mem_reserve + }; + + int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len, errp); + if (offset < 0) { + return offset; + } + + memcpy(dev->config + offset + PCI_CAP_FLAGS, + (char *)&cap + PCI_CAP_FLAGS, + cap_len - PCI_CAP_FLAGS); + return 0; +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ff7cbaa..be565f7 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -67,4 +67,25 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_n= ame, #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ =20 +typedef struct PCIBridgeQemuCap { + uint8_t id; /* Standard PCI capability header field */ + uint8_t next; /* Standard PCI capability header field */ + uint8_t len; /* Standard PCI vendor-specific capability header fiel= d */ + uint8_t type; /* Red Hat vendor-specific capability type. + Types are defined with REDHAT_PCI_CAP_ prefix */ + + uint32_t bus_res; /* Minimum number of buses to reserve */ + uint64_t io; /* IO space to reserve */ + uint64_t mem; /* Non-prefetchable memory to reserve */ + uint64_t mem_pref; /* Prefetchable memory to reserve */ +} PCIBridgeQemuCap; + +#define REDHAT_PCI_CAP_QEMU_RESERVE 1 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_reserve, + uint64_t non_pref_mem_reserve, + uint64_t pref_mem_reserve, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Wed May 1 19:38:54 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 150196490997278.56794642626357; Sat, 5 Aug 2017 13:28:29 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1de5dt-0004Fa-Ef; Sat, 05 Aug 2017 22:25:49 +0200 Received: from mail-lf0-f68.google.com ([209.85.215.68]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1de5di-0004Bo-TR for seabios@seabios.org; Sat, 05 Aug 2017 22:25:47 +0200 Received: by mail-lf0-f68.google.com with SMTP id o85so3072415lff.1 for ; Sat, 05 Aug 2017 13:28:01 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id e42sm1978197lji.81.2017.08.05.13.27.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:27:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m3SdUHPJL8WRuXpeNAb33JOqecIJfljP5LnmbJ84nEU=; b=nfe/q0TDyEOBFLYlVGHxzJc4FWfZNlrFyHb4CoShqWFjyFFzBEbgX34m+s3w0jP5gG +v3PmJPyL2ZNZpDKU9Iz1s9+785sBEKHzYDtX6HHRgaRskdxmn+RUgz3GpSEirm0jlD5 FMafDwxciXYPs+h81iwAJq8FuPvogGF0ETi8yZoJDc5yoEjMqUttT4so5LzxKvlm7R9y vCFeWuYurC14gQkPVMvipQijE/5eBkEGzlSBKTsRgRclb0S65i9MQ9CvnYA2q/8VKZo+ CriyDr5Y/s0oGL0ONgX1YdW3PNNfJ+PzutciZIiIhz/0eQzM/mZ0JvmN/ueRHdDePDSX qHcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m3SdUHPJL8WRuXpeNAb33JOqecIJfljP5LnmbJ84nEU=; b=SnnxEdXlp5lCSiWYQW7Bzvq0Ch8u0yq62qlZo27WO/vkjAEEoCnNUdIDcaN9XvItUw 5bVOPSELrumpZhtcpJkmwtk1JcA/NmZszJDsEjpsNrp0VoU/35kYx+boy4itnIpc7E+a x+/tmhlFUahMZb3nukd06cSbrQTdO2nhTkUYs02yy6qDVGeQDirx6c+qNzdrVP2e/TYh O1RnrMvcAFHLkQPH7Gxh+svsS0v7R/8AatIIr0TPN98QcS8t1Zd6F/pxFr1TDujzlgIU NOha2bJmrlVyZIUiWgrdMlArqreFXWjLfgDIG4JdgcfYGB999eIGZ9Q27aAB4sjUd6qG 46YQ== X-Gm-Message-State: AIVw113Xwbw/nA5JwAqp2NgFvqmNfQ2VeP/98GLnHVtANHXtI989F++5 EHXFtcxKxvf3RA== X-Received: by 10.46.87.81 with SMTP id r17mr2469621ljd.188.1501964880010; Sat, 05 Aug 2017 13:28:00 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 5 Aug 2017 23:27:37 +0300 Message-Id: <1501964858-5159-5-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> References: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -3.0 (---) Subject: [SeaBIOS] [PATCH v4 4/5] hw/pci: add QEMU-specific PCI capability to the Generic PCI Express Root Port X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (SeaBIOS in this case) to reserve additional buses or IO/MEM/PREF space for pcie-root-port. Additional bus reservation allows us to hotplug pcie-pci-bridge into this r= oot port. The number of buses to reserve is provided to the device via a corresponding property, and to the firmware via new PCI capability. The properties' default value is -1 to keep default behavior unchanged. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/pci-bridge/gen_pcie_root_port.c | 33 +++++++++++++++++++++++++++++++++ include/hw/pci/pcie_port.h | 1 + 2 files changed, 34 insertions(+) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index cb694d6..ff8d04c 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -16,6 +16,8 @@ #include "hw/pci/pcie_port.h" =20 #define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port" +#define GEN_PCIE_ROOT_PORT(obj) \ + OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT) =20 #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 @@ -26,6 +28,12 @@ typedef struct GenPCIERootPort { /*< public >*/ =20 bool migrate_msix; + + /* additional buses to reserve on firmware init */ + uint32_t bus_reserve; + uint64_t io_reserve; + uint64_t mem_reserve; + uint64_t pref_reserve; } GenPCIERootPort; =20 static uint8_t gen_rp_aer_vector(const PCIDevice *d) @@ -60,6 +68,23 @@ static bool gen_rp_test_migrate_msix(void *opaque, int v= ersion_id) return rp->migrate_msix; } =20 +static void gen_rp_realize(DeviceState *dev, Error **errp) +{ + PCIDevice *d =3D PCI_DEVICE(dev); + GenPCIERootPort *grp =3D GEN_PCIE_ROOT_PORT(d); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(d); + + rpc->parent_realize(dev, errp); + + int rc =3D pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve, + grp->io_reserve, grp->mem_reserve, grp->pref_reserve, errp); + + if (rc < 0) { + rpc->parent_class.exit(d); + return; + } +} + static const VMStateDescription vmstate_rp_dev =3D { .name =3D "pcie-root-port", .version_id =3D 1, @@ -78,6 +103,10 @@ static const VMStateDescription vmstate_rp_dev =3D { =20 static Property gen_rp_props[] =3D { DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true= ), + DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1), + DEFINE_PROP_UINT64("io-reserve", GenPCIERootPort, io_reserve, -1), + DEFINE_PROP_UINT64("mem-reserve", GenPCIERootPort, mem_reserve, -1), + DEFINE_PROP_UINT64("pref-reserve", GenPCIERootPort, pref_reserve, -1), DEFINE_PROP_END_OF_LIST() }; =20 @@ -92,6 +121,10 @@ static void gen_rp_dev_class_init(ObjectClass *klass, v= oid *data) dc->desc =3D "PCI Express Root Port"; dc->vmsd =3D &vmstate_rp_dev; dc->props =3D gen_rp_props; + + rpc->parent_realize =3D dc->realize; + dc->realize =3D gen_rp_realize; + rpc->aer_vector =3D gen_rp_aer_vector; rpc->interrupts_init =3D gen_rp_interrupts_init; rpc->interrupts_uninit =3D gen_rp_interrupts_uninit; diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 1333266..0736014 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -65,6 +65,7 @@ void pcie_chassis_del_slot(PCIESlot *s); =20 typedef struct PCIERootPortClass { PCIDeviceClass parent_class; + DeviceRealize parent_realize; =20 uint8_t (*aer_vector)(const PCIDevice *dev); int (*interrupts_init)(PCIDevice *dev, Error **errp); --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Wed May 1 19:38:54 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501964910337882.6539692002067; Sat, 5 Aug 2017 13:28:30 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1de5dx-0004II-Pl; Sat, 05 Aug 2017 22:25:53 +0200 Received: from mail-lf0-f65.google.com ([209.85.215.65]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1de5dl-0004C2-3V for seabios@seabios.org; Sat, 05 Aug 2017 22:25:52 +0200 Received: by mail-lf0-f65.google.com with SMTP id w199so3067154lff.2 for ; Sat, 05 Aug 2017 13:28:03 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id e42sm1978197lji.81.2017.08.05.13.28.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:28:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7P0s+htIFJbFRI6y1HKzhubVdF5S0JOiMiOwL2m2XeA=; b=m5WmGBJVQlFezt3pIAt0eIqO5ICEN7M+7sMkopF1Om91SXVqAq8/4kcLvrgozmXxCb jeByMWUOsC1amgngZVjEfYdKvdHOkfQ/YMUEDHpcxLL9kQFON9tcz9LNAVkGrP/KX87T 4/QwfPBHFuRwocGxhrw4pDTwAsmjr15MtAIYKtM6q/bqQo4hOeF0Fc4vQea8YwHaNW1i tXZ58eOjPdtPiKhTlktaAo7kMVnBBKSBJ2X00O4zwrwGgD1ng/tXfVM/Qaf9Geoy4+ky 23KUi5DEsRvaNd4synKNGt1/xve6bvsLBgnwQj3GUbHM4YgcFGOzZ0vzY4u6tVh18+pp NyYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7P0s+htIFJbFRI6y1HKzhubVdF5S0JOiMiOwL2m2XeA=; b=Sj/AXf+tZzcqrQL2dbVLlE0pvZzr8LKiiPqE6LudV/28aFu5k3UT5zKm9lAAw7jN+s 25omokZalQi4NppEmWU4bli8VwUPtlZbLG0aWygs5K2zXuROp9ct2T9KqDCZj2RanOHS rSlzBO7kRWBWR1PDzz0vs8pd1zcwhgRwfdKfR3GW+miklzs+EPhswqu43gYvqgJBL6uC JYUbl0+OrfoAA8kDuV+mg5hQlkY7rSWN4OYYCUkjvt8QCpiXPyMNltA7q51bKmtcPeHE OMptko+/JqMPCmsXVBk7KT6lDVCGbaCVTc++KTFByajLPRbQrkk1aTR9tmO7AcqJ2af2 2gaA== X-Gm-Message-State: AHYfb5hAk3uNfl0/QWlAabV64I9mLMrn9lsQoOQ4K2wOJgBUJDpxWobk COQK8R2SpsUO3g== X-Received: by 10.46.8.25 with SMTP id 25mr934632lji.39.1501964881990; Sat, 05 Aug 2017 13:28:01 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sat, 5 Aug 2017 23:27:38 +0300 Message-Id: <1501964858-5159-6-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> References: <1501964858-5159-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: 2.4 (++) Subject: [SeaBIOS] [PATCH v4 5/5] docs: update documentation considering PCIE-PCI bridge X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, lersek@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aleksandr Bezzubikov --- docs/pcie.txt | 49 +++++++++++---------- docs/pcie_pci_bridge.txt | 110 +++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 136 insertions(+), 23 deletions(-) create mode 100644 docs/pcie_pci_bridge.txt diff --git a/docs/pcie.txt b/docs/pcie.txt index 5bada24..76b85ec 100644 --- a/docs/pcie.txt +++ b/docs/pcie.txt @@ -46,7 +46,7 @@ Place only the following kinds of devices directly on the= Root Complex: (2) PCI Express Root Ports (ioh3420), for starting exclusively PCI Exp= ress hierarchies. =20 - (3) DMI-PCI Bridges (i82801b11-bridge), for starting legacy PCI + (3) PCI Express to PCI Bridge (pcie-pci-bridge), for starting legacy P= CI hierarchies. =20 (4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses @@ -55,18 +55,18 @@ Place only the following kinds of devices directly on t= he Root Complex: pcie.0 bus -----------------------------------------------------------------------= ----- | | | | - ----------- ------------------ ------------------ -------------- - | PCI Dev | | PCIe Root Port | | DMI-PCI Bridge | | pxb-pcie | - ----------- ------------------ ------------------ -------------- + ----------- ------------------ ------------------- -------------- + | PCI Dev | | PCIe Root Port | | PCIe-PCI Bridge | | pxb-pcie | + ----------- ------------------ ------------------- -------------- =20 2.1.1 To plug a device into pcie.0 as a Root Complex Integrated Endpoint u= se: -device [,bus=3Dpcie.0] 2.1.2 To expose a new PCI Express Root Bus use: -device pxb-pcie,id=3Dpcie.1,bus_nr=3Dx[,numa_node=3Dy][,addr=3D= z] - Only PCI Express Root Ports and DMI-PCI bridges can be connected - to the pcie.1 bus: + PCI Express Root Ports and PCI Express to PCI bridges can be + connected to the pcie.1 bus: -device ioh3420,id=3Droot_port1[,bus=3Dpcie.1][,chassis=3Dx][,sl= ot=3Dy][,addr=3Dz] \ - -device i82801b11-bridge,id=3Ddmi_pci_bridge1,bus=3Dpcie.1 + -device pcie-pci-bridge,id=3Dpcie_pci_bridge1,bus=3Dpcie.1 =20 =20 2.2 PCI Express only hierarchy @@ -130,24 +130,24 @@ Notes: Legacy PCI devices can be plugged into pcie.0 as Integrated Endpoints, but, as mentioned in section 5, doing so means the legacy PCI device in question will be incapable of hot-unplugging. -Besides that use DMI-PCI Bridges (i82801b11-bridge) in combination -with PCI-PCI Bridges (pci-bridge) to start PCI hierarchies. +Besides that use PCI Express to PCI Bridges (pcie-pci-bridge) in +combination with PCI-PCI Bridges (pci-bridge) to start PCI hierarchies. =20 -Prefer flat hierarchies. For most scenarios a single DMI-PCI Bridge +Prefer flat hierarchies. For most scenarios a single PCI Express to PCI Br= idge (having 32 slots) and several PCI-PCI Bridges attached to it (each supporting also 32 slots) will support hundreds of legacy devices. -The recommendation is to populate one PCI-PCI Bridge under the DMI-PCI Bri= dge -until is full and then plug a new PCI-PCI Bridge... +The recommendation is to populate one PCI-PCI Bridge under the +PCI Express to PCI Bridge until is full and then plug a new PCI-PCI Bridge= ... =20 pcie.0 bus ---------------------------------------------- | | - ----------- ------------------ - | PCI Dev | | DMI-PCI BRIDGE | - ---------- ------------------ + ----------- ------------------- + | PCI Dev | | PCIe-PCI Bridge | + ----------- ------------------- | | ------------------ ------------------ - | PCI-PCI Bridge | | PCI-PCI Bridge | ... + | PCI-PCI Bridge | | PCI-PCI Bridge | ------------------ ------------------ | | ----------- ----------- @@ -157,11 +157,11 @@ until is full and then plug a new PCI-PCI Bridge... 2.3.1 To plug a PCI device into pcie.0 as an Integrated Endpoint use: -device [,bus=3Dpcie.0] 2.3.2 Plugging a PCI device into a PCI-PCI Bridge: - -device i82801b11-bridge,id=3Ddmi_pci_bridge1[,bus=3Dpcie.0] = \ - -device pci-bridge,id=3Dpci_bridge1,bus=3Ddmi_pci_bridge1[,chassis_n= r=3Dx][,addr=3Dy] \ + -device pcie-pci-bridge,id=3Dpcie_pci_bridge1[,bus=3Dpcie.0] \ + -device pci-bridge,id=3Dpci_bridge1,bus=3Dpcie_pci_bridge1[,chassis_= nr=3Dx][,addr=3Dy] \ -device ,bus=3Dpci_bridge1[,addr=3Dx] Note that 'addr' cannot be 0 unless shpc=3Doff parameter is passed to - the PCI Bridge. + the PCI Bridge/PCI Express to PCI Bridge. =20 3. IO space issues =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -219,14 +219,16 @@ do not support hot-plug, so any devices plugged into = Root Complexes cannot be hot-plugged/hot-unplugged: (1) PCI Express Integrated Endpoints (2) PCI Express Root Ports - (3) DMI-PCI Bridges + (3) PCI Express to PCI Bridges (4) pxb-pcie =20 Be aware that PCI Express Downstream Ports can't be hot-plugged into an existing PCI Express Upstream Port. =20 -PCI devices can be hot-plugged into PCI-PCI Bridges. The PCI hot-plug is A= CPI -based and can work side by side with the PCI Express native hot-plug. +PCI devices can be hot-plugged into PCI Express to PCI and PCI-PCI Bridges. +The PCI hot-plug into PCI-PCI bridge is ACPI based, whereas hot-plug into +PCI Express to PCI bridges is SHPC-based. They both can work side by side = with +the PCI Express native hot-plug. =20 PCI Express devices can be natively hot-plugged/hot-unplugged into/from PCI Express Root Ports (and PCI Express Downstream Ports). @@ -234,10 +236,11 @@ PCI Express Root Ports (and PCI Express Downstream Po= rts). 5.1 Planning for hot-plug: (1) PCI hierarchy Leave enough PCI-PCI Bridge slots empty or add one - or more empty PCI-PCI Bridges to the DMI-PCI Bridge. + or more empty PCI-PCI Bridges to the PCI Express to PCI Bridge. =20 For each such PCI-PCI Bridge the Guest Firmware is expected to res= erve 4K IO space and 2M MMIO range to be used for all devices behind it. + Appropriate PCI capability is designed, see pcie_pci_bridge.txt. =20 Because of the hard IO limit of around 10 PCI Bridges (~ 40K space) per system don't use more than 9 PCI-PCI Bridges, leaving 4K for t= he diff --git a/docs/pcie_pci_bridge.txt b/docs/pcie_pci_bridge.txt new file mode 100644 index 0000000..89d6754 --- /dev/null +++ b/docs/pcie_pci_bridge.txt @@ -0,0 +1,110 @@ +Generic PCI Express to PCI Bridge +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +Description +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +PCIE-to-PCI bridge is a new method for legacy PCI +hierarchies creation on Q35 machines. + +Previously Intel DMI-to-PCI bridge was used for this purpose. +But due to its strict limitations - no support of hot-plug, +no cross-platform and cross-architecture support - a new generic +PCIE-to-PCI bridge should now be used for any legacy PCI device usage +with PCI Express machine. + +This generic PCIE-PCI bridge is a cross-platform device, +can be hot-plugged into appropriate root port (requires additional actions, +see 'PCIE-PCI bridge hot-plug' section), +and supports devices hot-plug into the bridge itself +(with some limitations, see below). + +Hot-plug of legacy PCI devices into the bridge +is provided by bridge's built-in Standard hot-plug Controller. +Though it still has some limitations, see below. + +PCIE-PCI bridge hot-plug +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Guest OSes require extra efforts to enable PCIE-PCI bridge hot-plug. +Motivation - now on init any PCI Express root port which doesn't have +any device plugged in, has no free buses reserved to provide any of them +to a hot-plugged devices in future. + +To solve this problem we reserve additional buses on a firmware level. +Currently only SeaBIOS is supported. +The way of bus number to reserve delivery is special +Red Hat vendor-specific PCI capability, added to the root port +that is planned to have PCIE-PCI bridge hot-plugged in. + +Capability layout (defined in include/hw/pci/pci_bridge.h): + + uint8_t id; Standard PCI capability header field + uint8_t next; Standard PCI capability header field + uint8_t len; Standard PCI vendor-specific capability header field + + uint8_t type; Red Hat vendor-specific capability type + List of currently existing types: + QEMU_RESERVE =3D 1 + + + uint32_t bus_res; Minimum number of buses to reserve + + uint64_t io; IO space to reserve + uint64_t mem Non-prefetchable memory to reserve + uint64_t mem_pref; Prefetchable memory to reserve + +If any reservation field is equal to -1 then this kind of reservation is n= ot +needed and must be ignored by firmware. + +At the moment this capability is used only in QEMU generic PCIe root port +(-device pcie-root-port). Capability construction function takes all reser= vation +fields values from corresponding device properties. By default all of them= are +set to -1 to leave root port's default behavior unchanged. + +Usage +=3D=3D=3D=3D=3D +A detailed command line would be: + +[qemu-bin + storage options] \ +-m 2G \ +-device ioh3420,bus=3Dpcie.0,id=3Drp1 \ +-device ioh3420,bus=3Dpcie.0,id=3Drp2 \ +-device pcie-root-port,bus=3Dpcie.0,id=3Drp3,bus-reserve=3D1 \ +-device pcie-pci-bridge,id=3Dbr1,bus=3Drp1 \ +-device pcie-pci-bridge,id=3Dbr2,bus=3Drp2 \ +-device e1000,bus=3Dbr1,addr=3D8 + +Then in monitor it's OK to execute next commands: +device_add pcie-pci-bridge,id=3Dbr3,bus=3Drp3 +device_add e1000,bus=3Dbr2,addr=3D1 +device_add e1000,bus=3Dbr3,addr=3D1 + +Here you have: + (1) Cold-plugged: + - Root ports: 1 QEMU generic root port with the capability mentioned a= bove, + 2 ioh3420 root ports; + - 2 PCIE-PCI bridges plugged into 2 different root ports; + - e1000 plugged into the first bridge. + (2) Hot-plugged: + - PCIE-PCI bridge, plugged into QEMU generic root port; + - 2 e1000 cards, one plugged into the cold-plugged PCIE-PCI bridge, + another plugged into the hot-plugged bridge. + +Limitations +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The PCIE-PCI bridge can be hot-plugged only into pcie-root-port that +has proper 'bus-reserve' property value to provide secondary bus for the +hot-plugged bridge. + +Windows 7 and older versions don't support hot-plug devices into the PCIE-= PCI bridge. +To enable device hot-plug into the bridge on Linux there're 3 ways: +1) Build shpchp module with this patch http://www.spinics.net/lists/linux-= pci/msg63052.html +2) Use kernel 4.14+ where the patch mentioned above is already merged. +3) Set 'msi' property to off - this forced the bridge to use legacy INTx, + which allows the bridge to notify the OS about hot-plug event without = having + BUSMASTER set. + +Implementation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The PCIE-PCI bridge is based on PCI-PCI bridge, but also accumulates PCI E= xpress +features as a PCI Express device (is_express=3D1). + --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios