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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=43.163.128.47; envelope-from=yfliu2008@qq.com; helo=xmbghk7.mail.qq.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qq.com) X-ZM-MESSAGEID: 1782630397747158500 Content-Type: text/plain; charset="utf-8" This adds secondary UART device to RiscV virt board to simplify multi-core bare-metal development as Virtio needs comparably more work. Signed-off-by: Yanfeng Liu --- hw/riscv/virt.c | 33 +++++++++++++++++++++++---------- include/hw/riscv/virt.h | 2 ++ 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 33775a61fd..d414953d6f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -86,6 +86,7 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_MROM] =3D { 0x1000, 0xf000 }, [VIRT_TEST] =3D { 0x100000, 0x1000 }, [VIRT_RTC] =3D { 0x101000, 0x1000 }, + [VIRT_UART1] =3D { 0x102000, 0x100 }, [VIRT_CLINT] =3D { 0x2000000, 0x10000 }, [VIRT_ACLINT_SSWI] =3D { 0x2F00000, 0x4000 }, [VIRT_PCIE_PIO] =3D { 0x3000000, 0x10000 }, @@ -186,7 +187,8 @@ static void create_pcie_irq_map(RISCVVirtState *s, void= *fdt, char *nodename, FDT_MAX_INT_MAP_WIDTH] =3D {}; uint32_t *irq_map =3D full_irq_map; =20 - /* This code creates a standard swizzle of interrupts such that + /* + * This code creates a standard swizzle of interrupts such that * each device's first interrupt is based on it's PCI_SLOT number. * (See pci_swizzle_map_irq_fn()) * @@ -832,28 +834,36 @@ static void create_fdt_reset(RISCVVirtState *s, uint3= 2_t *phandle) } =20 static void create_fdt_uart(RISCVVirtState *s, - uint32_t irq_mmio_phandle) + uint32_t irq_mmio_phandle, int memId, int irqN= o) { g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); =20 name =3D g_strdup_printf("/soc/serial@%"HWADDR_PRIx, - s->memmap[VIRT_UART0].base); + s->memmap[memId].base); qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", - 2, s->memmap[VIRT_UART0].base, - 2, s->memmap[VIRT_UART0].size); + 2, s->memmap[memId].base, + 2, s->memmap[memId].size); qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phan= dle); if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", irqNo); } else { - qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4= ); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", irqNo, 0x4); } =20 - qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); - qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); + if (VIRT_UART0 =3D=3D memId) { + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); + qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); + } +} + +static void create_fdt_uarts(RISCVVirtState *s, uint32_t irq_mmio_phandle) +{ + create_fdt_uart(s, irq_mmio_phandle, VIRT_UART0, UART0_IRQ); + create_fdt_uart(s, irq_mmio_phandle, VIRT_UART1, UART1_IRQ); } =20 static void create_fdt_rtc(RISCVVirtState *s, @@ -1023,7 +1033,7 @@ static void finalize_fdt(RISCVVirtState *s) =20 create_fdt_reset(s, &phandle); =20 - create_fdt_uart(s, irq_mmio_phandle); + create_fdt_uarts(s, irq_mmio_phandle); =20 create_fdt_rtc(s, irq_mmio_phandle); } @@ -1566,6 +1576,9 @@ static void virt_machine_init(MachineState *machine) serial_mm_init(system_memory, s->memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); + serial_mm_init(system_memory, s->memmap[VIRT_UART1].base, + 0, qdev_get_gpio_in(mmio_irqchip, UART1_IRQ), 399193, + serial_hd(1), DEVICE_LITTLE_ENDIAN); =20 sysbus_create_simple("goldfish_rtc", s->memmap[VIRT_RTC].base, qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 18a2a323a3..d27bab9f64 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -78,6 +78,7 @@ enum { VIRT_APLIC_S, VIRT_UART0, VIRT_VIRTIO, + VIRT_UART1, VIRT_FW_CFG, VIRT_IMSIC_M, VIRT_IMSIC_S, @@ -93,6 +94,7 @@ enum { enum { UART0_IRQ =3D 10, RTC_IRQ =3D 11, + UART1_IRQ =3D 12, VIRTIO_IRQ =3D 1, /* 1 to 8 */ VIRTIO_COUNT =3D 8, PCIE_IRQ =3D 0x20, /* 32 to 35 */ --=20 2.34.1