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[37.6.160.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d437a5sm366348766b.101.2024.08.04.14.04.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Aug 2024 14:04:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722805467; x=1723410267; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SJdRSPH/xM+z+0nBRsC0mklzYhlrkNq7AnAF+TlID90=; b=Retpld+z+59Uqn2O/7xXetnLaeaFPaLOrl/bH71LYZldSTuNdvv9GxF5Iz+0z1fm+y bvTjaEbhZ3ZjIrqhMwIwzWYAMS5DaBPuuRQ9VIRgMDc5t2YdC8PcZSCLUZPD5B+GkKoM hYdcbHYfS8eKzRB14Sir6WZrBzT8Dal8fp/+SeV5yLJ2Y5dzdlCRwgFGbWrBVk5SheHo +VcJQtTh+mAL7HRUrsLJnQD3pXed0+rG8/PpSmwfQzJh/705E2Y5IkAiTWdW7tLIQYlC gjb38jFNTxrj7qQ3ZHfBYjz7yUPvHgFH6+D23wNODbdXU2THSYui2Sh8WIFQP9819cB5 WMqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722805467; x=1723410267; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SJdRSPH/xM+z+0nBRsC0mklzYhlrkNq7AnAF+TlID90=; b=hAqsgVNizcTwoQ4eu+6S2BBsE7cp3dklRVueqkh3N5KX9/ry3izrGucTXowz4T2Zq5 jgg9sULoOvgceg7C67zZm9ADLKEnutKglrCqL+UZPzGJQMb/sTaQvwbXPgXR1GpRRpvc o4714ZdEOGD1E96BrFtlZToU6d19mFAnzfpqnBejxse2NDYzdtLhKWH0Ov00IoFyoYxk qZNeP5OSQhjgZQCpgRgEnZ1J9S8DMEVkIn26diS/V5s3r/ocXduEw4ZzHZ3p9iiAvOZa X+GetYfP7oFEzNUI5an6RL7bIMuKxd/1Ei2FRyKqFQWEqJnbcImlzjLOcb0dM1tgC87h W5RQ== X-Gm-Message-State: AOJu0YwZYaTgWPGMaVVE/ZGWaJ79rXqPGMje8X9mRkiCL0WztJRYNv8D j2xDUI/RYdXfULoGJ/s3aim4GhKGgG89LeqHpsRQ5xkTC3vzrgRnOHYMLHH9+xuLfUTGbIDvvHL GsCI= X-Google-Smtp-Source: AGHT+IHLrzRKSDJ9fRV+g5xcL34fSL0kHNh1jHH1EEvxeNX+jmPPzFvr6PbwK44eYb5u+4leEsmvtA== X-Received: by 2002:a17:907:6e86:b0:a72:8d2f:859c with SMTP id a640c23a62f3a-a7dc4fd88fbmr676558266b.33.1722805467044; Sun, 04 Aug 2024 14:04:27 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson , Paolo Bonzini Subject: [RFC PATCH v6 1/5] build-sys: Add rust feature option Date: Mon, 5 Aug 2024 00:04:12 +0300 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1722805540493116600 Content-Type: text/plain; charset="utf-8" Add rust feature in meson.build, configure, to prepare for adding Rust code in the followup commits. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 5 +++++ configure | 2 ++ meson.build | 25 ++++++++++++++++++++++++- Kconfig | 1 + Kconfig.host | 3 +++ meson_options.txt | 3 +++ rust/Kconfig | 0 scripts/meson-buildoptions.sh | 3 +++ 8 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 rust/Kconfig diff --git a/MAINTAINERS b/MAINTAINERS index e34c2bd4cd..4ba57c9c67 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4239,6 +4239,11 @@ F: docs/sphinx/ F: docs/_templates/ F: docs/devel/docs.rst =20 +Rust build system integration +M: Manos Pitsidianakis +S: Maintained +F: rust/Kconfig + Miscellaneous ------------- Performance Tools and Tests diff --git a/configure b/configure index 019fcbd0ef..aac7f29f25 100755 --- a/configure +++ b/configure @@ -874,6 +874,8 @@ Advanced options (experts only): start the emulator (only use if you are includi= ng desired devices in configs/devices/) --with-devices-ARCH=3DNAME override default configs/devices + --enable-rust enable compilation of Rust code + --disable-rust disable compilation of Rust code --enable-debug enable common debug build options --cpu=3DCPU Build for host CPU [$cpu] --disable-containers don't use containers for cross-building diff --git a/meson.build b/meson.build index 97f63aa86c..9593fce47f 100644 --- a/meson.build +++ b/meson.build @@ -70,6 +70,22 @@ if host_os =3D=3D 'darwin' and \ all_languages +=3D ['objc'] objc =3D meson.get_compiler('objc') endif +if get_option('rust').enabled() and meson.version().version_compare('<1.0.= 0') + error('Rust support requires Meson version >=3D1.0.0') +endif +have_rust =3D false +if not get_option('rust').disabled() and add_languages('rust', required: g= et_option('rust'), native: false) + rustc =3D meson.get_compiler('rust') + have_rust =3D true + if rustc.version().version_compare('<1.80.0') + if get_option('rust').enabled() + error('rustc version ' + rustc.version() + ' is unsupported: Please = upgrade to at least 1.80.0') + else + warning('rustc version ' + rustc.version() + ' is unsupported: Disab= ling Rust compilation. Please upgrade to at least 1.80.0 to use Rust.') + have_rust =3D false + endif + endif +endif =20 dtrace =3D not_found stap =3D not_found @@ -2119,6 +2135,7 @@ endif =20 config_host_data =3D configuration_data() =20 +config_host_data.set('CONFIG_HAVE_RUST', have_rust) audio_drivers_selected =3D [] if have_system audio_drivers_available =3D { @@ -3062,7 +3079,8 @@ host_kconfig =3D \ (host_os =3D=3D 'linux' ? ['CONFIG_LINUX=3Dy'] : []) + \ (multiprocess_allowed ? ['CONFIG_MULTIPROCESS_ALLOWED=3Dy'] : []) + \ (vfio_user_server_allowed ? ['CONFIG_VFIO_USER_SERVER_ALLOWED=3Dy'] : []= ) + \ - (hv_balloon ? ['CONFIG_HV_BALLOON_POSSIBLE=3Dy'] : []) + (hv_balloon ? ['CONFIG_HV_BALLOON_POSSIBLE=3Dy'] : []) + \ + (have_rust ? ['CONFIG_HAVE_RUST=3Dy'] : []) =20 ignored =3D [ 'TARGET_XML_FILES', 'TARGET_ABI_DIR', 'TARGET_ARCH' ] =20 @@ -4273,6 +4291,11 @@ if 'objc' in all_languages else summary_info +=3D {'Objective-C compiler': false} endif +summary_info +=3D {'Rust support': have_rust} +if have_rust + summary_info +=3D {'rustc version': rustc.version()} + summary_info +=3D {'rustc': ' '.join(rustc.cmd_array())} +endif option_cflags =3D (get_option('debug') ? ['-g'] : []) if get_option('optimization') !=3D 'plain' option_cflags +=3D ['-O' + get_option('optimization')] diff --git a/Kconfig b/Kconfig index fb6a24a2de..63ca7f46df 100644 --- a/Kconfig +++ b/Kconfig @@ -4,3 +4,4 @@ source accel/Kconfig source target/Kconfig source hw/Kconfig source semihosting/Kconfig +source rust/Kconfig diff --git a/Kconfig.host b/Kconfig.host index 17f405004b..4ade7899d6 100644 --- a/Kconfig.host +++ b/Kconfig.host @@ -52,3 +52,6 @@ config VFIO_USER_SERVER_ALLOWED =20 config HV_BALLOON_POSSIBLE bool + +config HAVE_RUST + bool diff --git a/meson_options.txt b/meson_options.txt index 0269fa0f16..fa94a5ce97 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -371,3 +371,6 @@ option('hexagon_idef_parser', type : 'boolean', value := true, =20 option('x86_version', type : 'combo', choices : ['0', '1', '2', '3', '4'],= value: '1', description: 'tweak required x86_64 architecture version beyond com= piler default') + +option('rust', type: 'feature', value: 'auto', + description: 'Rust support') diff --git a/rust/Kconfig b/rust/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index c97079a38c..5e8a225a6b 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -170,6 +170,7 @@ meson_options_help() { printf "%s\n" ' rbd Ceph block device driver' printf "%s\n" ' rdma Enable RDMA-based migration' printf "%s\n" ' replication replication support' + printf "%s\n" ' rust Rust support' printf "%s\n" ' rutabaga-gfx rutabaga_gfx support' printf "%s\n" ' sdl SDL user interface' printf "%s\n" ' sdl-image SDL Image support for icons' @@ -452,6 +453,8 @@ _meson_option_parse() { --disable-replication) printf "%s" -Dreplication=3Ddisabled ;; --enable-rng-none) printf "%s" -Drng_none=3Dtrue ;; --disable-rng-none) printf "%s" -Drng_none=3Dfalse ;; + --enable-rust) printf "%s" -Drust=3Denabled ;; + --disable-rust) printf "%s" -Drust=3Ddisabled ;; --enable-rutabaga-gfx) printf "%s" -Drutabaga_gfx=3Denabled ;; --disable-rutabaga-gfx) printf "%s" -Drutabaga_gfx=3Ddisabled ;; --enable-safe-stack) printf "%s" -Dsafe_stack=3Dtrue ;; --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89 From nobody Sun Nov 24 12:39:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1722805545; cv=none; d=zohomail.com; s=zohoarc; b=oI1E0x3/tjTn1FE3JQB2/TifgLD/UAyC6QHplKBlO7Jsq9mftYkQZxZOwDRfMZsPyf+0/Nnwhk5wkDClzizW2HBl1rwVySU7oY5TAzKLdHQL2CSEwwDjHUYuU9iICYNYkfC6jzqPWzylvCsoEdCwAY4wBAG8I6ufidxK678S8Mc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1722805545; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Qn3mGXnmhMG+A80ZK0JJrAwRkG85xoS/9ALggp/piZw=; b=ICr8FF+GpkrBb9Fmv3jm8lAM2yLtM7nfryjVzOdjkeVjosvoMACwYKel+h3fbbwa44jp8SYFt8rft3VhNqgLMV09+4aGxfjJfXGea1mV8wclETZrnKInTf4ZcOi0WGof3Fq2ATgGQ7OYykcpuSapDK06JtvwLT7kCNvPZLsYexM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1722805545704926.0496108952427; Sun, 4 Aug 2024 14:05:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1saiP7-0008SU-6k; Sun, 04 Aug 2024 17:04:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1saiP4-0008Jk-J3 for qemu-devel@nongnu.org; Sun, 04 Aug 2024 17:04:34 -0400 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1saiP2-0005fQ-9v for qemu-devel@nongnu.org; Sun, 04 Aug 2024 17:04:34 -0400 Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-5b8c2a6135dso2455246a12.1 for ; Sun, 04 Aug 2024 14:04:31 -0700 (PDT) Received: from localhost.localdomain (adsl-146.37.6.160.tellas.gr. [37.6.160.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d437a5sm366348766b.101.2024.08.04.14.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Aug 2024 14:04:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722805470; x=1723410270; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qn3mGXnmhMG+A80ZK0JJrAwRkG85xoS/9ALggp/piZw=; b=BB/UL84eLTL9EoHAsgnh6jDpVsqiESApbORMhMkoHTqwzJ5InwelDPu90L5iEgQ875 7HWNRzEkRv3zNvWN5mZ7IEkty3UDu4fZyjUmXZrCoooTafAhV1LkDJbGD0i4fE6UX9Hu ExD17tE7Bzlsaq+P5HO9vfNRKBm66uXNnG9iYEio0AupHeIquayjUWmqKmc28rwZwC24 wPOOu3TsGyzGwz7FNGiSBJ2hMBM1wHHhOZGbrDLdHEY8/LoBr4cAS/K2x0/DMj1u17EX Zzr4GrgJdcKBJ2FtoDrqbYELWIOH/eyKliUr9WbssdEckuU24haEiogQORt9HJRIHtnw 7n5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722805470; x=1723410270; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qn3mGXnmhMG+A80ZK0JJrAwRkG85xoS/9ALggp/piZw=; b=D2+1P6r1hvYTWzUufJP6YOVIpvyBQIyDm0oj+8NKx+ggp3ey/5CGv4dA5kmfWF2/GN A3GSNa9YYKHWfj9t5QOlGccZYHeB5H7UW+fRCOgXZJ1gY02ZkSofZ/y6IYrEoNe5Y8OY rmYFHVFk0NKr+7CPrdaS0BVPZEuB9X6UTeKC6bfVpKwCj1ukFBKD3D1xHpwq9T66rGtZ LH9ZDyNYcZjfO16E2ok3+0MZIgHGzbHcJ8kYUi08SewKSgtoE/EFIHGZ8bxLURIJ2OL1 MirirOWvG6thaIpPXfnxotVml/LaZgKOTEJUrf/27h8IrbbLBKd857oA5u92YN/oTklZ L2YQ== X-Gm-Message-State: AOJu0YwaljT/GXrZvqU5TbHnGXt8TgI+6It080pt197R7Lxt9A+A7TJ2 PbV/INpCXoe+jHkNzTu8qE2ik1LLtidfxx4/kvHXVvzNMwE2hoLI5JhlIuw3Q0Gqmc9Siyo2my7 tizQ= X-Google-Smtp-Source: AGHT+IGa59LpJgQBXELaYgbxPhCUCt1hOaWVb6AbDpSr/jRKbue1ra1/Z9V8HKT+JhuSSXVqxrd0Ew== X-Received: by 2002:a17:906:d247:b0:a7a:a763:8438 with SMTP id a640c23a62f3a-a7dc509f93fmr651553566b.55.1722805470346; Sun, 04 Aug 2024 14:04:30 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson , Paolo Bonzini , John Snow , Cleber Rosa Subject: [RFC PATCH v6 2/5] rust: add bindgen step as a meson dependency Date: Mon, 5 Aug 2024 00:04:13 +0300 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1722805546355116600 Content-Type: text/plain; charset="utf-8" Add bindings_rs target for generating rust bindings to target-independent qemu C APIs. The bindings need be created before any rust crate that uses them is compiled. The bindings.rs file will end up in BUILDDIR/bindings.rs and have the same name as a target: ninja bindings.rs Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 4 +++ meson.build | 52 +++++++++++++++++++++++++++ rust/wrapper.h | 39 ++++++++++++++++++++ rust/.gitignore | 3 ++ rust/meson.build | 0 scripts/rustc_args.py | 84 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 182 insertions(+) create mode 100644 rust/wrapper.h create mode 100644 rust/.gitignore create mode 100644 rust/meson.build create mode 100644 scripts/rustc_args.py diff --git a/MAINTAINERS b/MAINTAINERS index 4ba57c9c67..e1d77816bb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4242,7 +4242,11 @@ F: docs/devel/docs.rst Rust build system integration M: Manos Pitsidianakis S: Maintained +F: scripts/rustc_args.py +F: rust/.gitignore F: rust/Kconfig +F: rust/meson.build +F: rust/wrapper.h =20 Miscellaneous ------------- diff --git a/meson.build b/meson.build index 9593fce47f..19f32bb67c 100644 --- a/meson.build +++ b/meson.build @@ -306,6 +306,15 @@ foreach lang : all_languages endif endforeach =20 +if have_rust + rust_args =3D [] + if get_option('debug') + rust_args +=3D ['-g'] + endif + if get_option('optimization') not in ['0', '1', 'g'] + rust_args +=3D ['-O'] + endif +endif # default flags for all hosts # We use -fwrapv to tell the compiler that we require a C dialect where # left shift of signed integers is well defined and has the expected @@ -3860,6 +3869,49 @@ common_all =3D static_library('common', implicit_include_directories: false, dependencies: common_ss.all_dependencies()) =20 +if have_rust and have_system + rust_args +=3D run_command( + meson.global_source_root() / 'scripts/rustc_args.py', + '--config-headers', meson.project_build_root() / 'config-host.h', + capture : true, + check: true).stdout().strip().split() + + bindings_rs =3D import('rust').bindgen( + input: 'rust/wrapper.h', + dependencies: common_ss.all_dependencies(), + output: 'bindings.rs', + include_directories: include_directories('.', 'include'), + bindgen_version: ['>=3D0.69.4'], + args: [ + '--raw-line', '#![allow(dead_code)]', + '--raw-line', '#![allow(non_camel_case_types)]', + '--raw-line', '#![allow(non_snake_case)]', + '--raw-line', '#![allow(non_upper_case_globals)]', + '--raw-line', '#![allow(improper_ctypes_definitions)]', + '--raw-line', '#![allow(improper_ctypes)]', + '--raw-line', 'unsafe impl Send for Property {}', + '--raw-line', 'unsafe impl Sync for Property {}', + '--raw-line', 'unsafe impl Sync for TypeInfo {}', + '--raw-line', 'unsafe impl Sync for VMStateDescription {}', + '--ctypes-prefix', 'core::ffi', + '--formatter', 'rustfmt', + '--generate-block', + '--generate-cstr', + '--impl-debug', + '--merge-extern-blocks', + '--no-doc-comments', + '--no-include-path-detection', + '--use-core', + '--with-derive-default', + '--allowlist-file', meson.project_source_root() + '/include/.*', + '--allowlist-file', meson.project_source_root() + '/.*', + '--allowlist-file', meson.project_build_root() + '/.*' + ], + ) + subdir('rust') +endif + + feature_to_c =3D find_program('scripts/feature_to_c.py') =20 if host_os =3D=3D 'darwin' diff --git a/rust/wrapper.h b/rust/wrapper.h new file mode 100644 index 0000000000..51985f0ef1 --- /dev/null +++ b/rust/wrapper.h @@ -0,0 +1,39 @@ +/* + * QEMU System Emulator + * + * Copyright 2024 Manos Pitsidianakis + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "qemu-io.h" +#include "sysemu/sysemu.h" +#include "hw/sysbus.h" +#include "exec/memory.h" +#include "chardev/char-fe.h" +#include "hw/clock.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "hw/irq.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "chardev/char-serial.h" diff --git a/rust/.gitignore b/rust/.gitignore new file mode 100644 index 0000000000..1bf71b1f68 --- /dev/null +++ b/rust/.gitignore @@ -0,0 +1,3 @@ +# Ignore any cargo development build artifacts; for qemu-wide builds, all = build +# artifacts will go to the meson build directory. +target diff --git a/rust/meson.build b/rust/meson.build new file mode 100644 index 0000000000..e69de29bb2 diff --git a/scripts/rustc_args.py b/scripts/rustc_args.py new file mode 100644 index 0000000000..e4cc9720e1 --- /dev/null +++ b/scripts/rustc_args.py @@ -0,0 +1,84 @@ +#!/usr/bin/env python3 + +"""Generate rustc arguments for meson rust builds. + +This program generates --cfg compile flags for the configuration headers p= assed +as arguments. + +Copyright (c) 2024 Linaro Ltd. + +Authors: + Manos Pitsidianakis + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . +""" + +import argparse +import logging + +from typing import List + + +def generate_cfg_flags(header: str) -> List[str]: + """Converts defines from config[..].h headers to rustc --cfg flags.""" + + def cfg_name(name: str) -> str: + """Filter function for C #defines""" + if ( + name.startswith("CONFIG_") + or name.startswith("TARGET_") + or name.startswith("HAVE_") + ): + return name + return "" + + with open(header, encoding=3D"utf-8") as cfg: + config =3D [l.split()[1:] for l in cfg if l.startswith("#define")] + + cfg_list =3D [] + for cfg in config: + name =3D cfg_name(cfg[0]) + if not name: + continue + if len(cfg) >=3D 2 and cfg[1] !=3D "1": + continue + cfg_list.append("--cfg") + cfg_list.append(name) + return cfg_list + + +def main() -> None: + # pylint: disable=3Dmissing-function-docstring + parser =3D argparse.ArgumentParser() + parser.add_argument("-v", "--verbose", action=3D"store_true") + parser.add_argument( + "--config-headers", + metavar=3D"CONFIG_HEADER", + action=3D"append", + dest=3D"config_headers", + help=3D"paths to any configuration C headers (*.h files), if any", + required=3DFalse, + default=3D[], + ) + args =3D parser.parse_args() + if args.verbose: + logging.basicConfig(level=3Dlogging.DEBUG) + logging.debug("args: %s", args) + for header in args.config_headers: + for tok in generate_cfg_flags(header): + print(tok) + + +if __name__ =3D=3D "__main__": + main() --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89 From nobody Sun Nov 24 12:39:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1722805551; cv=none; d=zohomail.com; s=zohoarc; b=YIR71CnEN0HJ+4Z2V7euxNm98mkUz9Qh2DTjdjq9kq6mQGVIzsIE8lDYzN8kEkJj87zV0n7V8YC9GSdz8RgOqUZeMnc9+1FdYTAieIVNaxq4q6ATrRfW44Y2bHfQqYUIgDdF66/NfuFph8osBQ41YsPZX75Cllo2JQmNMKSG698= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1722805551; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TXjCGVQS/+hcLwTR+qUNdXq2a9N5/772SuBnlrJC6HA=; b=mhjii/EKhZO4n+T9CQWew3rGNs0S14lYHYowsUAqiDP4o/7A4VeIDiNaMGsSQRJmXAaWum2+nIcMdQdgPGUL7IZXIVn/B5vM5QHULGv6+QYStm/gcnmZ7a3RxHj+RiJbYyN9D02QUutXOzelWFnsyoSpcMYaIx0xy5XNslVIh0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172280555180675.06941144968926; Sun, 4 Aug 2024 14:05:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1saiP6-0008Qo-DE; Sun, 04 Aug 2024 17:04:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1saiP5-0008OB-N5 for qemu-devel@nongnu.org; Sun, 04 Aug 2024 17:04:35 -0400 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1saiP4-0005gD-8K for qemu-devel@nongnu.org; Sun, 04 Aug 2024 17:04:35 -0400 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-a7de4364ca8so141865066b.2 for ; Sun, 04 Aug 2024 14:04:33 -0700 (PDT) Received: from localhost.localdomain (adsl-146.37.6.160.tellas.gr. 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[37.6.160.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d437a5sm366348766b.101.2024.08.04.14.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Aug 2024 14:04:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722805476; x=1723410276; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y6xSCc8EwwqNsiFZtSpuPg4nSUYRHEdWi3cZTUJR6L0=; b=LnqqUIuPahfQy1l8I7vd2kFrjuZFNtCHtyRMLnO4Z3TsnTXOQQY5f/031LfWORT9+9 s/zrVMV7w+lKLMUnRA778LSDDjV+lSWyoEedf1r8yBq7G891DIYv10698N32WJHGu+NQ jKfKFF1VH2w+DpGIv0+tKEW4PMvZWk5/V89qPkUjdzU3dnj06qVfApY5k08X3u14FHYc hQkB/XwC4lUkxCP5rNRUMDm0IoChenp0EnKnmtDAvh/bn/QuoBNsMFsbq2I/1buUomRu mshLfjOiuaJol23wiyYjEzFKCpOeKeo4DzYsNWhx1kRtJA91mmSGH/8FI5n6CDmQ/fH8 +6AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722805476; x=1723410276; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y6xSCc8EwwqNsiFZtSpuPg4nSUYRHEdWi3cZTUJR6L0=; b=w3zGWoxhL/pnyZuagDlGZmVkxv/7IJZcve/zFq2EQnHS3RbZnJwyrqWRJWygw82sDf F9ufztwa/0yoX3D+dMwoGc7JXcS1EomxbnKZrIra/sRidr5sQydcjboZeaP/N7ZLsOmy UYJRB4A/+AmBNF+iVg0tQ77jTq4rzZO9r0D45Yf5p+dLmuxT0rPm7rTpSyA8RGderWZE z4YyaoSuFrB5km3Eni26EiFX8dp+ZS+4ES3qv1hjCIG2di244JDA8k7tGrMsjKOXqG/M 7rYu7RWLwjkpkhTkJIVX/Spex9awIr5YjRIEUC9pDkBhxJySHmIGe26Y6SuDU8y64M0q eqOw== X-Gm-Message-State: AOJu0YxOxO7iRUHcpDgzv+R27pFb19Xth3PqNwnBntWY736hEyg6Bbut DyVj9cGTaUYrweEImjQDHppGjKfpXycukXO3xYCW76SLPeMoHI2N8G3ef3jHLDVM02QADNeMBTx Vs7E= X-Google-Smtp-Source: AGHT+IGZ3+I5l9yKHIgL6qqkUHkIdiP3hPsb38u23m8tjCDaJlGO6W8V2L0lMAaAGG7+bSrbZQT9Xw== X-Received: by 2002:ac2:4e07:0:b0:52c:ce28:82c8 with SMTP id 2adb3069b0e04-530bb4d6cc3mr6660288e87.52.1722805475215; Sun, 04 Aug 2024 14:04:35 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson Subject: [RFC PATCH v6 4/5] rust: add crate to expose bindings and interfaces Date: Mon, 5 Aug 2024 00:04:15 +0300 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1722805524300116600 Content-Type: text/plain; charset="utf-8" Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and provides some declaration macros for symbols visible to the rest of QEMU. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 6 ++ rust/meson.build | 13 +++ rust/qemu-api/.gitignore | 2 + rust/qemu-api/Cargo.lock | 7 ++ rust/qemu-api/Cargo.toml | 23 ++++++ rust/qemu-api/README.md | 17 ++++ rust/qemu-api/build.rs | 13 +++ rust/qemu-api/meson.build | 19 +++++ rust/qemu-api/rustfmt.toml | 1 + rust/qemu-api/src/bindings.rs | 7 ++ rust/qemu-api/src/definitions.rs | 108 +++++++++++++++++++++++++ rust/qemu-api/src/device_class.rs | 128 ++++++++++++++++++++++++++++++ rust/qemu-api/src/lib.rs | 100 +++++++++++++++++++++++ rust/qemu-api/src/tests.rs | 48 +++++++++++ rust/rustfmt.toml | 7 ++ 15 files changed, 499 insertions(+) create mode 100644 rust/qemu-api/.gitignore create mode 100644 rust/qemu-api/Cargo.lock create mode 100644 rust/qemu-api/Cargo.toml create mode 100644 rust/qemu-api/README.md create mode 100644 rust/qemu-api/build.rs create mode 100644 rust/qemu-api/meson.build create mode 120000 rust/qemu-api/rustfmt.toml create mode 100644 rust/qemu-api/src/bindings.rs create mode 100644 rust/qemu-api/src/definitions.rs create mode 100644 rust/qemu-api/src/device_class.rs create mode 100644 rust/qemu-api/src/lib.rs create mode 100644 rust/qemu-api/src/tests.rs create mode 100644 rust/rustfmt.toml diff --git a/MAINTAINERS b/MAINTAINERS index e1d77816bb..018f3a9420 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3345,6 +3345,12 @@ F: hw/core/register.c F: include/hw/register.h F: include/hw/registerfields.h =20 +Rust +M: Manos Pitsidianakis +S: Maintained +F: rust/qemu-api +F: rust/rustfmt.toml + SLIRP M: Samuel Thibault S: Maintained diff --git a/rust/meson.build b/rust/meson.build index e69de29bb2..a903c7c602 100644 --- a/rust/meson.build +++ b/rust/meson.build @@ -0,0 +1,13 @@ +add_languages('rust', required: true) + +_lib_bindings_rs =3D static_library( + '_bindings_rs', + bindings_rs, + gnu_symbol_visibility: 'hidden', + rust_abi: 'rust', + rust_args: rust_args + [ + '--edition', '2021', + ], +) + +subdir('qemu-api') diff --git a/rust/qemu-api/.gitignore b/rust/qemu-api/.gitignore new file mode 100644 index 0000000000..71eaff2035 --- /dev/null +++ b/rust/qemu-api/.gitignore @@ -0,0 +1,2 @@ +# Ignore generated bindings file overrides. +src/bindings.rs.inc diff --git a/rust/qemu-api/Cargo.lock b/rust/qemu-api/Cargo.lock new file mode 100644 index 0000000000..e9c51a243a --- /dev/null +++ b/rust/qemu-api/Cargo.lock @@ -0,0 +1,7 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version =3D 3 + +[[package]] +name =3D "qemu_api" +version =3D "0.1.0" diff --git a/rust/qemu-api/Cargo.toml b/rust/qemu-api/Cargo.toml new file mode 100644 index 0000000000..51260cbe42 --- /dev/null +++ b/rust/qemu-api/Cargo.toml @@ -0,0 +1,23 @@ +[package] +name =3D "qemu_api" +version =3D "0.1.0" +edition =3D "2021" +authors =3D ["Manos Pitsidianakis "] +license =3D "GPL-2.0 OR GPL-3.0-or-later" +readme =3D "README.md" +homepage =3D "https://www.qemu.org" +description =3D "Rust bindings for QEMU" +repository =3D "https://gitlab.com/qemu-project/qemu/" +resolver =3D "2" +publish =3D false +keywords =3D [] +categories =3D [] + +[dependencies] + +[features] +default =3D ["allocator"] +allocator =3D [] + +# Do not include in any global workspace +[workspace] diff --git a/rust/qemu-api/README.md b/rust/qemu-api/README.md new file mode 100644 index 0000000000..7588fa29ef --- /dev/null +++ b/rust/qemu-api/README.md @@ -0,0 +1,17 @@ +# QEMU bindings and API wrappers + +This library exports helper Rust types, Rust macros and C FFI bindings for= internal QEMU APIs. + +The C bindings can be generated with `bindgen`, using this build target: + +```console +$ ninja bindings.rs +``` + +## Generate Rust documentation + +To generate docs for this crate, including private items: + +```sh +cargo doc --no-deps --document-private-items +``` diff --git a/rust/qemu-api/build.rs b/rust/qemu-api/build.rs new file mode 100644 index 0000000000..2f57c2b3d4 --- /dev/null +++ b/rust/qemu-api/build.rs @@ -0,0 +1,13 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use std::path::Path; + +fn main() { + if !Path::new("src/bindings.rs.inc").exists() { + panic!( + "No generated C bindings found! Either build them manually wit= h bindgen or with meson \ + (`ninja bindings.rs`) and copy them to src/bindings.rs.inc, o= r build through meson." + ); + } +} diff --git a/rust/qemu-api/meson.build b/rust/qemu-api/meson.build new file mode 100644 index 0000000000..7992dc64ce --- /dev/null +++ b/rust/qemu-api/meson.build @@ -0,0 +1,19 @@ +add_languages('rust', required: true) + +_qemu_api_rs =3D static_library( + 'qemu_api', + [files('src/lib.rs')], + gnu_symbol_visibility: 'hidden', + rust_abi: 'rust', + rust_args: rust_args + [ + '--edition', '2021', + '--cfg', 'MESON_BINDINGS_RS', + ], + link_with: [ + _lib_bindings_rs, + ], +) + +qemu_api =3D declare_dependency( + link_with: _qemu_api_rs, +) diff --git a/rust/qemu-api/rustfmt.toml b/rust/qemu-api/rustfmt.toml new file mode 120000 index 0000000000..39f97b043b --- /dev/null +++ b/rust/qemu-api/rustfmt.toml @@ -0,0 +1 @@ +../rustfmt.toml \ No newline at end of file diff --git a/rust/qemu-api/src/bindings.rs b/rust/qemu-api/src/bindings.rs new file mode 100644 index 0000000000..fb595f1469 --- /dev/null +++ b/rust/qemu-api/src/bindings.rs @@ -0,0 +1,7 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later +#[cfg(not(MESON_BINDINGS_RS))] +include!("bindings.rs.inc"); + +#[cfg(MESON_BINDINGS_RS)] +pub use ::_bindings_rs::*; diff --git a/rust/qemu-api/src/definitions.rs b/rust/qemu-api/src/definitio= ns.rs new file mode 100644 index 0000000000..6de42229b6 --- /dev/null +++ b/rust/qemu-api/src/definitions.rs @@ -0,0 +1,108 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +//! Definitions required by QEMU when registering a device. + +/// Trait a type must implement to be registered with QEMU. +pub trait ObjectImpl { + type Class; + const TYPE_INFO: crate::bindings::TypeInfo; + const TYPE_NAME: &'static ::core::ffi::CStr; + const PARENT_TYPE_NAME: Option<&'static ::core::ffi::CStr>; + const INSTANCE_INIT: ::core::option::Option< + unsafe extern "C" fn(obj: *mut crate::bindings::Object), + >; + const INSTANCE_POST_INIT: ::core::option::Option< + unsafe extern "C" fn(obj: *mut crate::bindings::Object), + >; + const INSTANCE_FINALIZE: ::core::option::Option< + unsafe extern "C" fn(obj: *mut crate::bindings::Object), + >; + const ABSTRACT: bool; +} + +pub trait Class { + const CLASS_INIT: ::core::option::Option< + unsafe extern "C" fn( + klass: *mut crate::bindings::ObjectClass, + data: *mut core::ffi::c_void, + ), + >; + const CLASS_BASE_INIT: ::core::option::Option< + unsafe extern "C" fn( + klass: *mut crate::bindings::ObjectClass, + data: *mut core::ffi::c_void, + ), + >; +} + +#[macro_export] +macro_rules! module_init { + ($func:expr, $type:expr) =3D> { + #[used] + #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] + #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] + #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] + pub static LOAD_MODULE: extern "C" fn() =3D { + assert!($type < $crate::bindings::module_init_type_MODULE_INIT= _MAX); + + extern "C" fn __load() { + unsafe { + $crate::bindings::register_module_init(Some($func), $t= ype); + } + } + + __load + }; + }; + (qom: $func:ident =3D> $body:block) =3D> { + // NOTE: To have custom identifiers for the ctor func we need to e= ither supply + // them directly as a macro argument or create them with a proc ma= cro. + #[used] + #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] + #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] + #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] + pub static LOAD_MODULE: extern "C" fn() =3D { + extern "C" fn __load() { + #[no_mangle] + unsafe extern "C" fn $func() { + $body + } + + unsafe { + $crate::bindings::register_module_init( + Some($func), + $crate::bindings::module_init_type_MODULE_INIT_QOM, + ); + } + } + + __load + }; + }; +} + +#[macro_export] +macro_rules! type_info { + ($t:ty) =3D> { + $crate::bindings::TypeInfo { + name: <$t as $crate::definitions::ObjectImpl>::TYPE_NAME.as_pt= r(), + parent: if let Some(pname) =3D <$t as $crate::definitions::Obj= ectImpl>::PARENT_TYPE_NAME { + pname.as_ptr() + } else { + ::core::ptr::null_mut() + }, + instance_size: ::core::mem::size_of::<$t>(), + instance_align: ::core::mem::align_of::<$t>(), + instance_init: <$t as $crate::definitions::ObjectImpl>::INSTAN= CE_INIT, + instance_post_init: <$t as $crate::definitions::ObjectImpl>::I= NSTANCE_POST_INIT, + instance_finalize: <$t as $crate::definitions::ObjectImpl>::IN= STANCE_FINALIZE, + abstract_: <$t as $crate::definitions::ObjectImpl>::ABSTRACT, + class_size: ::core::mem::size_of::<<$t as $crate::definitions= ::ObjectImpl>::Class>(), + class_init: <<$t as $crate::definitions::ObjectImpl>::Class as= $crate::definitions::Class>::CLASS_INIT, + class_base_init: <<$t as $crate::definitions::ObjectImpl>::Cla= ss as $crate::definitions::Class>::CLASS_BASE_INIT, + class_data: ::core::ptr::null_mut(), + interfaces: ::core::ptr::null_mut(), + }; + } +} diff --git a/rust/qemu-api/src/device_class.rs b/rust/qemu-api/src/device_c= lass.rs new file mode 100644 index 0000000000..f8d4c04e03 --- /dev/null +++ b/rust/qemu-api/src/device_class.rs @@ -0,0 +1,128 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use std::sync::OnceLock; + +use crate::bindings::Property; + +#[macro_export] +macro_rules! device_class_init { + ($func:ident, props =3D> $props:ident, realize_fn =3D> $realize_fn:exp= r, reset_fn =3D> $reset_fn:expr, vmsd =3D> $vmsd:ident$(,)*) =3D> { + #[no_mangle] + pub unsafe extern "C" fn $func( + klass: *mut $crate::bindings::ObjectClass, + _: *mut ::core::ffi::c_void, + ) { + let mut dc =3D + ::core::ptr::NonNull::new(klass.cast::<$crate::bindings::D= eviceClass>()).unwrap(); + dc.as_mut().realize =3D $realize_fn; + dc.as_mut().reset =3D $reset_fn; + dc.as_mut().vmsd =3D &$vmsd; + $crate::bindings::device_class_set_props(dc.as_mut(), $props.a= s_mut_ptr()); + } + }; +} + +#[macro_export] +macro_rules! define_property { + ($name:expr, $state:ty, $field:expr, $prop:expr, $type:expr, default = =3D $defval:expr$(,)*) =3D> { + $crate::bindings::Property { + name: { + #[used] + static _TEMP: &::core::ffi::CStr =3D $name; + _TEMP.as_ptr() + }, + info: $prop, + offset: ::core::mem::offset_of!($state, $field) + .try_into() + .expect("Could not fit offset value to type"), + bitnr: 0, + bitmask: 0, + set_default: true, + defval: $crate::bindings::Property__bindgen_ty_1 { u: $defval.= into() }, + arrayoffset: 0, + arrayinfo: ::core::ptr::null(), + arrayfieldsize: 0, + link_type: ::core::ptr::null(), + } + }; + ($name:expr, $state:ty, $field:expr, $prop:expr, $type:expr$(,)*) =3D>= { + $crate::bindings::Property { + name: { + #[used] + static _TEMP: &::core::ffi::CStr =3D $name; + _TEMP.as_ptr() + }, + info: $prop, + offset: ::core::mem::offset_of!($state, $field) + .try_into() + .expect("Could not fit offset value to type"), + bitnr: 0, + bitmask: 0, + set_default: false, + defval: $crate::bindings::Property__bindgen_ty_1 { i: 0 }, + arrayoffset: 0, + arrayinfo: ::core::ptr::null(), + arrayfieldsize: 0, + link_type: ::core::ptr::null(), + } + }; +} + +#[repr(C)] +pub struct Properties(pub OnceLock<[Property; N]>, pub fn(= ) -> [Property; N]); + +impl Properties { + pub fn as_mut_ptr(&mut self) -> *mut Property { + _ =3D self.0.get_or_init(self.1); + self.0.get_mut().unwrap().as_mut_ptr() + } +} + +#[macro_export] +macro_rules! declare_properties { + ($ident:ident, $($prop:expr),*$(,)*) =3D> { + + const fn _calc_prop_len() -> usize { + let mut len =3D 1; + $({ + _ =3D stringify!($prop); + len +=3D 1; + })* + len + } + const PROP_LEN: usize =3D _calc_prop_len(); + + #[no_mangle] + fn _make_properties() -> [$crate::bindings::Property; PROP_LEN] { + [ + $($prop),*, + unsafe { ::core::mem::MaybeUninit::<$crate::bindings::= Property>::zeroed().assume_init() }, + ] + } + + #[no_mangle] + pub static mut $ident: $crate::device_class::Properties = =3D $crate::device_class::Properties(::std::sync::OnceLock::new(), _make_pr= operties); + }; +} + +#[macro_export] +macro_rules! vm_state_description { + ($(#[$outer:meta])* + $name:ident, + $(name: $vname:expr,)* + $(unmigratable: $um_val:expr,)* + ) =3D> { + #[used] + $(#[$outer])* + pub static $name: $crate::bindings::VMStateDescription =3D $crate:= :bindings::VMStateDescription { + $(name: { + #[used] + static VMSTATE_NAME: &::core::ffi::CStr =3D $vname; + $vname.as_ptr() + },)* + unmigratable: true, + ..unsafe { ::core::mem::MaybeUninit::<$crate::bindings::VMStat= eDescription>::zeroed().assume_init() } + }; + } +} diff --git a/rust/qemu-api/src/lib.rs b/rust/qemu-api/src/lib.rs new file mode 100644 index 0000000000..6f02ac45e2 --- /dev/null +++ b/rust/qemu-api/src/lib.rs @@ -0,0 +1,100 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +#![doc =3D include_str!("../README.md")] + +#[cfg(MESON_BINDINGS_RS)] +extern crate _bindings_rs; + +#[cfg_attr(not(MESON_BINDINGS_RS), allow( + improper_ctypes_definitions, + improper_ctypes, + non_camel_case_types, + non_snake_case, + non_upper_case_globals +))] +#[cfg_attr(not(MESON_BINDINGS_RS), allow( + clippy::missing_const_for_fn, + clippy::too_many_arguments, + clippy::approx_constant, + clippy::use_self, + clippy::useless_transmute, + clippy::missing_safety_doc, +))] +#[cfg_attr(not(MESON_BINDINGS_RS), rustfmt::skip)] +pub mod bindings; + +pub mod definitions; +pub mod device_class; + +#[cfg(test)] +mod tests; + +use std::alloc::{GlobalAlloc, Layout}; + +extern "C" { + pub fn g_aligned_alloc0( + n_blocks: bindings::gsize, + n_block_bytes: bindings::gsize, + alignment: bindings::gsize, + ) -> bindings::gpointer; + pub fn g_aligned_free(mem: bindings::gpointer); + pub fn g_malloc0(n_bytes: bindings::gsize) -> bindings::gpointer; + pub fn g_free(mem: bindings::gpointer); +} + +/// An allocator that uses the same allocator as QEMU in C. +/// +/// It is enabled by default with the `allocator` feature. +/// +/// To set it up manually as a global allocator in your crate: +/// +/// ```ignore +/// use qemu_api::QemuAllocator; +/// +/// #[global_allocator] +/// static GLOBAL: QemuAllocator =3D QemuAllocator::new(); +/// ``` +#[derive(Clone, Copy, Debug)] +#[repr(C)] +pub struct QemuAllocator { + _unused: [u8; 0], +} + +#[cfg_attr(feature =3D "allocator", global_allocator)] +pub static GLOBAL: QemuAllocator =3D QemuAllocator::new(); + +impl QemuAllocator { + pub const fn new() -> Self { + Self { _unused: [] } + } +} + +impl Default for QemuAllocator { + fn default() -> Self { + Self::new() + } +} + +unsafe impl GlobalAlloc for QemuAllocator { + unsafe fn alloc(&self, layout: Layout) -> *mut u8 { + if layout.align() =3D=3D 0 { + g_malloc0(layout.size().try_into().unwrap()).cast::() + } else { + g_aligned_alloc0( + layout.size().try_into().unwrap(), + 1, + layout.align().try_into().unwrap(), + ) + .cast::() + } + } + + unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) { + if layout.align() =3D=3D 0 { + g_free(ptr.cast::<_>()) + } else { + g_aligned_free(ptr.cast::<_>()) + } + } +} diff --git a/rust/qemu-api/src/tests.rs b/rust/qemu-api/src/tests.rs new file mode 100644 index 0000000000..88c26308ee --- /dev/null +++ b/rust/qemu-api/src/tests.rs @@ -0,0 +1,48 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use crate::{ + bindings::*, declare_properties, define_property, device_class_init, v= m_state_description, +}; + +#[test] +fn test_device_decl_macros() { + // Test that macros can compile. + vm_state_description! { + VMSTATE, + name: c"name", + unmigratable: true, + } + + #[repr(C)] + pub struct DummyState { + pub char_backend: CharBackend, + pub migrate_clock: bool, + } + + declare_properties! { + DUMMY_PROPERTIES, + define_property!( + c"chardev", + DummyState, + char_backend, + unsafe { &qdev_prop_chr }, + CharBackend + ), + define_property!( + c"migrate-clk", + DummyState, + migrate_clock, + unsafe { &qdev_prop_bool }, + bool + ), + } + + device_class_init! { + dummy_class_init, + props =3D> DUMMY_PROPERTIES, + realize_fn =3D> None, + reset_fn =3D> None, + vmsd =3D> VMSTATE, + } +} diff --git a/rust/rustfmt.toml b/rust/rustfmt.toml new file mode 100644 index 0000000000..ebecb99fe0 --- /dev/null +++ b/rust/rustfmt.toml @@ -0,0 +1,7 @@ +edition =3D "2021" +format_generated_files =3D false +format_code_in_doc_comments =3D true +format_strings =3D true +imports_granularity =3D "Crate" +group_imports =3D "StdExternalCrate" +wrap_comments =3D true --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89 From nobody Sun Nov 24 12:39:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1722805544; cv=none; d=zohomail.com; s=zohoarc; b=inlQZsusaKD7lMMT0pG+IitSY/qbj+QP6Jyp3gRJ7g9FtBsFuTB6eoyfdTFwf6V3h8Tp0ARraDuKhnWswCFIX4m+DqXUkp8yxgpGWHRtDkCps29soCiaRjf34aIAWngd8Pnw/KHVo2FdgxzFzt8EVjzkB0JogioCoa4hpmUZGXM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1722805544; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q0tXcCXJohj8h7cWfoRrfKhlyjeqU/qsIHPq7f62cRA=; b=CvXtb6z/locKhbruKG1r8UdbnUGPdq6AU0cN6fEZU3kZNRHqrXQhFFXjjnVx0IYIYdhtzgZp3SVmt8FNsm23jFsSfjUcN4nPSYD4dUkOrT1SXgYLk9cgT1pKvLaMmcO6TI0T9KQ3CSUPGW1wca1xRGtZeIJTOMTXSgYQDW6dtLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1722805544202196.3968543374192; Sun, 4 Aug 2024 14:05:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1saiPI-0000fL-3G; Sun, 04 Aug 2024 17:04:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1saiPG-0000bo-1D for qemu-devel@nongnu.org; Sun, 04 Aug 2024 17:04:46 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1saiPB-0005ib-3y for qemu-devel@nongnu.org; Sun, 04 Aug 2024 17:04:45 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-a7a8caef11fso1135951866b.0 for ; Sun, 04 Aug 2024 14:04:40 -0700 (PDT) Received: from localhost.localdomain (adsl-146.37.6.160.tellas.gr. [37.6.160.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d437a5sm366348766b.101.2024.08.04.14.04.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Aug 2024 14:04:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1722805479; x=1723410279; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q0tXcCXJohj8h7cWfoRrfKhlyjeqU/qsIHPq7f62cRA=; b=O49gOdmjRiBVPYNU+b3wUjHsEa7jCy4n4VRxLbnR5t34t4lCo9Z8XfOTakwFk81QD3 vUFHQjBaojYdziRReNoqrnHGc5AVP5oFHfg+d9RNyvfD8qpMX6gFuUaahUicVXwkTiBT JmdmtML/vbNiXGRsy23eEONcyOsIuxQy5mHzg6ZtS2mfqypM/97k1dmGdqfDe1zA3gJD ifSz0sD4aQwHq2HxkVJK0TyEfON/uHhyrNl0qn4B3jDGIi4EYptUgVNHma0KzmIhZP+J uc9zjXbcZaT2fvEdS4/AM83KUUOQqO0uuVYDjEgbCyIu4V1D7EIAJ8zALK76M+HgE+9k DW2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722805479; x=1723410279; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q0tXcCXJohj8h7cWfoRrfKhlyjeqU/qsIHPq7f62cRA=; b=Xh8CQ1vrcI+Vq2ASQ9+SBIuxoBpdX8EgkbI1CXM547BSx6+kPZs2+JzxeSAS7+vMVM 4swqf4en0G2nUUhI4Mpbs+zjiBtSld6+9emA3FL/1MCK+y62fe2mBG17kjiHyQhu04O6 bE0EIE0EF8TwRFGQyU6KGys9qmagFKrTfjakiHe56ck0EWqt2Av3dtjxCdNqnvpC9MAa g/u5zNJTPXVfGEdMP3H+xehnHUmvaZo0W3TS4zIFBgXE45oZq8Md3h8dFvw2+Vo0E2Bp gMDRL6DDkcvep8skaBZaJqHjhyUew1BNKELVwDB8nmgZ2Ybu9J7fdtz5kqvKR1v07x4z DAOw== X-Gm-Message-State: AOJu0YzTJFEu1ErgdDbTBeh8GT5dZ4kwoKgu/T2ftKn9wPiLKO8AH6+S xE4Y6vtlm1imAHwcHhX8tRhhCbAx/VVRiZOwh0AyYqGxagnTKB2kqG50OFtmGW/9XPD0r8TySlu 1vAU= X-Google-Smtp-Source: AGHT+IEeKrsaZKVcxT19X3LB1n3AM9XfY47zROT3dEinfqBEOJlJ1VsKO3aQcI6B9sTJMFPyaUJAAA== X-Received: by 2002:a17:907:9707:b0:a77:c043:5b5a with SMTP id a640c23a62f3a-a7dc4ffee29mr731137666b.39.1722805478539; Sun, 04 Aug 2024 14:04:38 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson , Paolo Bonzini , qemu-arm@nongnu.org Subject: [RFC PATCH v6 5/5] rust: add PL011 device model Date: Mon, 5 Aug 2024 00:04:16 +0300 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1722805546367116600 Content-Type: text/plain; charset="utf-8" This commit adds a re-implementation of hw/char/pl011.c in Rust. How to build: 1. Configure a QEMU build with: --enable-system --target-list=3Daarch64-softmmu --enable-rust 2. Launching a VM with qemu-system-aarch64 should use the Rust version of the pl011 device Signed-off-by: Manos Pitsidianakis --- Note: subproject dependencies licenses are not correct. --- MAINTAINERS | 5 + hw/arm/Kconfig | 33 +- rust/Kconfig | 1 + rust/hw/Kconfig | 2 + rust/hw/char/Kconfig | 3 + rust/hw/char/meson.build | 1 + rust/hw/char/pl011/.gitignore | 2 + rust/hw/char/pl011/Cargo.lock | 125 ++++ rust/hw/char/pl011/Cargo.toml | 26 + rust/hw/char/pl011/README.md | 31 + rust/hw/char/pl011/meson.build | 28 + rust/hw/char/pl011/rustfmt.toml | 1 + rust/hw/char/pl011/src/definitions.rs | 26 + rust/hw/char/pl011/src/device.rs | 586 ++++++++++++++++++ rust/hw/char/pl011/src/device_class.rs | 58 ++ rust/hw/char/pl011/src/lib.rs | 584 +++++++++++++++++ rust/hw/char/pl011/src/memory_ops.rs | 56 ++ rust/hw/meson.build | 1 + rust/meson.build | 2 + subprojects/.gitignore | 11 + subprojects/arbitrary-int.wrap | 9 + subprojects/bilge-impl.wrap | 10 + subprojects/bilge.wrap | 10 + subprojects/either.wrap | 10 + subprojects/itertools.wrap | 10 + .../packagefiles/arbitrary-int/meson.build | 19 + .../packagefiles/bilge-impl/meson.build | 36 ++ subprojects/packagefiles/bilge/meson.build | 25 + subprojects/packagefiles/either/meson.build | 21 + .../packagefiles/itertools/meson.build | 25 + .../proc-macro-error-attr/meson.build | 27 + .../packagefiles/proc-macro-error/meson.build | 32 + .../packagefiles/proc-macro2/meson.build | 26 + subprojects/packagefiles/quote/meson.build | 25 + subprojects/packagefiles/syn/meson.build | 33 + .../packagefiles/unicode-ident/meson.build | 19 + subprojects/proc-macro-error-attr.wrap | 10 + subprojects/proc-macro-error.wrap | 11 + subprojects/proc-macro2.wrap | 10 + subprojects/quote.wrap | 10 + subprojects/syn.wrap | 11 + subprojects/unicode-ident.wrap | 10 + 42 files changed, 1970 insertions(+), 11 deletions(-) create mode 100644 rust/hw/Kconfig create mode 100644 rust/hw/char/Kconfig create mode 100644 rust/hw/char/meson.build create mode 100644 rust/hw/char/pl011/.gitignore create mode 100644 rust/hw/char/pl011/Cargo.lock create mode 100644 rust/hw/char/pl011/Cargo.toml create mode 100644 rust/hw/char/pl011/README.md create mode 100644 rust/hw/char/pl011/meson.build create mode 120000 rust/hw/char/pl011/rustfmt.toml create mode 100644 rust/hw/char/pl011/src/definitions.rs create mode 100644 rust/hw/char/pl011/src/device.rs create mode 100644 rust/hw/char/pl011/src/device_class.rs create mode 100644 rust/hw/char/pl011/src/lib.rs create mode 100644 rust/hw/char/pl011/src/memory_ops.rs create mode 100644 rust/hw/meson.build create mode 100644 subprojects/arbitrary-int.wrap create mode 100644 subprojects/bilge-impl.wrap create mode 100644 subprojects/bilge.wrap create mode 100644 subprojects/either.wrap create mode 100644 subprojects/itertools.wrap create mode 100644 subprojects/packagefiles/arbitrary-int/meson.build create mode 100644 subprojects/packagefiles/bilge-impl/meson.build create mode 100644 subprojects/packagefiles/bilge/meson.build create mode 100644 subprojects/packagefiles/either/meson.build create mode 100644 subprojects/packagefiles/itertools/meson.build create mode 100644 subprojects/packagefiles/proc-macro-error-attr/meson.bu= ild create mode 100644 subprojects/packagefiles/proc-macro-error/meson.build create mode 100644 subprojects/packagefiles/proc-macro2/meson.build create mode 100644 subprojects/packagefiles/quote/meson.build create mode 100644 subprojects/packagefiles/syn/meson.build create mode 100644 subprojects/packagefiles/unicode-ident/meson.build create mode 100644 subprojects/proc-macro-error-attr.wrap create mode 100644 subprojects/proc-macro-error.wrap create mode 100644 subprojects/proc-macro2.wrap create mode 100644 subprojects/quote.wrap create mode 100644 subprojects/syn.wrap create mode 100644 subprojects/unicode-ident.wrap diff --git a/MAINTAINERS b/MAINTAINERS index 018f3a9420..2b3d96fa2f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1188,6 +1188,11 @@ F: include/hw/*/microbit*.h F: tests/qtest/microbit-test.c F: docs/system/arm/nrf.rst =20 +ARM PL011 Rust device +M: Manos Pitsidianakis +S: Maintained +F: rust/hw/char/pl011/ + AVR Machines ------------- =20 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 1ad60da7aa..45438c1bc4 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -20,7 +20,8 @@ config ARM_VIRT select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL061 # GPIO select GPIO_PWR @@ -80,7 +81,8 @@ config HIGHBANK select AHCI select ARM_TIMER # sp804 select ARM_V7M - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL022 # SPI select PL031 # RTC select PL061 # GPIO @@ -93,7 +95,8 @@ config INTEGRATOR depends on TCG && ARM select ARM_TIMER select INTEGRATOR_DEBUG - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL041 # audio select PL050 # keyboard/mouse @@ -119,7 +122,8 @@ config MUSCA default y depends on TCG && ARM select ARMSSE - select PL011 + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 select SPLIT_IRQ select UNIMP @@ -228,7 +232,8 @@ config Z2 depends on TCG && ARM select PFLASH_CFI01 select WM8750 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PXA2XX =20 config REALVIEW @@ -248,7 +253,8 @@ config REALVIEW select WM8750 # audio codec select LSI_SCSI_PCI select PCI - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL041 # audio codec select PL050 # keyboard/mouse @@ -273,7 +279,8 @@ config SBSA_REF select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL031 # RTC select PL061 # GPIO select USB_XHCI_SYSBUS @@ -297,7 +304,8 @@ config STELLARIS select ARM_V7M select CMSDK_APB_WATCHDOG select I2C - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL022 # SPI select PL061 # GPIO select SSD0303 # OLED display @@ -356,7 +364,8 @@ config VEXPRESS select ARM_TIMER # sp804 select LAN9118 select PFLASH_CFI01 - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select PL041 # audio codec select PL181 # display select REALVIEW @@ -440,7 +449,8 @@ config RASPI default y depends on TCG && ARM select FRAMEBUFFER - select PL011 # UART + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select SDHCI select USB_DWC2 select BCM2835_SPI @@ -515,7 +525,8 @@ config XLNX_VERSAL select ARM_GIC select CPU_CLUSTER select DEVICE_TREE - select PL011 + select PL011 if !HAVE_RUST # UART + select X_PL011_RUST if HAVE_RUST # UART select CADENCE select VIRTIO_MMIO select UNIMP diff --git a/rust/Kconfig b/rust/Kconfig index e69de29bb2..f9f5c39098 100644 --- a/rust/Kconfig +++ b/rust/Kconfig @@ -0,0 +1 @@ +source hw/Kconfig diff --git a/rust/hw/Kconfig b/rust/hw/Kconfig new file mode 100644 index 0000000000..4d934f30af --- /dev/null +++ b/rust/hw/Kconfig @@ -0,0 +1,2 @@ +# devices Kconfig +source char/Kconfig diff --git a/rust/hw/char/Kconfig b/rust/hw/char/Kconfig new file mode 100644 index 0000000000..a1732a9e97 --- /dev/null +++ b/rust/hw/char/Kconfig @@ -0,0 +1,3 @@ +config X_PL011_RUST + bool + default y if HAVE_RUST diff --git a/rust/hw/char/meson.build b/rust/hw/char/meson.build new file mode 100644 index 0000000000..5716dc43ef --- /dev/null +++ b/rust/hw/char/meson.build @@ -0,0 +1 @@ +subdir('pl011') diff --git a/rust/hw/char/pl011/.gitignore b/rust/hw/char/pl011/.gitignore new file mode 100644 index 0000000000..71eaff2035 --- /dev/null +++ b/rust/hw/char/pl011/.gitignore @@ -0,0 +1,2 @@ +# Ignore generated bindings file overrides. +src/bindings.rs.inc diff --git a/rust/hw/char/pl011/Cargo.lock b/rust/hw/char/pl011/Cargo.lock new file mode 100644 index 0000000000..411bfed9c9 --- /dev/null +++ b/rust/hw/char/pl011/Cargo.lock @@ -0,0 +1,125 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version =3D 3 + +[[package]] +name =3D "arbitrary-int" +version =3D "1.2.7" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c84fc003e338a6f69fbd4f7fe9f92b535ff13e9af8997f3b14b6ddff8b1d= f46d" + +[[package]] +name =3D "bilge" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "dc707ed8ebf81de5cd6c7f48f54b4c8621760926cdf35a57000747c512e6= 7b57" +dependencies =3D [ + "arbitrary-int", + "bilge-impl", +] + +[[package]] +name =3D "bilge-impl" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D 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"registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cd= cff5" +dependencies =3D [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name =3D "unicode-ident" +version =3D "1.0.12" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0f= ee4b" + +[[package]] +name =3D "version_check" +version =3D "0.9.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e= 483f" diff --git a/rust/hw/char/pl011/Cargo.toml b/rust/hw/char/pl011/Cargo.toml new file mode 100644 index 0000000000..67a6973da6 --- /dev/null +++ b/rust/hw/char/pl011/Cargo.toml @@ -0,0 +1,26 @@ +[package] +name =3D "pl011" +version =3D "0.1.0" +edition =3D "2021" +authors =3D ["Manos Pitsidianakis "] +license =3D "GPL-2.0 OR GPL-3.0-or-later" +readme =3D "README.md" +homepage =3D "https://www.qemu.org" +description =3D "pl011 device model for QEMU" +repository =3D "https://gitlab.com/epilys/rust-for-qemu" +resolver =3D "2" +publish =3D false +keywords =3D [] +categories =3D [] + +[lib] +crate-type =3D ["staticlib"] + +[dependencies] +arbitrary-int =3D { version =3D "1.2.7" } +bilge =3D { version =3D "0.2.0" } +bilge-impl =3D { version =3D "0.2.0" } +qemu_api =3D { path =3D "../../../qemu-api" } + +# Do not include in any global workspace +[workspace] diff --git a/rust/hw/char/pl011/README.md b/rust/hw/char/pl011/README.md new file mode 100644 index 0000000000..cd7dea3163 --- /dev/null +++ b/rust/hw/char/pl011/README.md @@ -0,0 +1,31 @@ +# PL011 QEMU Device Model + +This library implements a device model for the PrimeCell=C2=AE UART (PL011) +device in QEMU. + +## Build static lib + +Host build target must be explicitly specified: + +```sh +cargo build --target x86_64-unknown-linux-gnu +``` + +Replace host target triplet if necessary. + +## Generate Rust documentation + +To generate docs for this crate, including private items: + +```sh +cargo doc --no-deps --document-private-items --target x86_64-unknown-linux= -gnu +``` + +To include direct dependencies like `bilge` (bitmaps for register types): + +```sh +cargo tree --depth 1 -e normal --prefix none \ + | cut -d' ' -f1 \ + | xargs printf -- '-p %s\n' \ + | xargs cargo doc --no-deps --document-private-items --target x86_64-unkn= own-linux-gnu +``` diff --git a/rust/hw/char/pl011/meson.build b/rust/hw/char/pl011/meson.build new file mode 100644 index 0000000000..a17a823cf5 --- /dev/null +++ b/rust/hw/char/pl011/meson.build @@ -0,0 +1,28 @@ +if not config_host_data.get('CONFIG_HAVE_RUST') + subdir_done() +endif + +add_languages('rust', required: true) + + +arbitrary_int_dep =3D subproject('arbitrary-int').get_variable('arbitrary_= int_dep') +bilge_dep =3D subproject('bilge').get_variable('bilge_dep') +bilge_impl_dep =3D subproject('bilge-impl').get_variable('bilge_impl_dep') + +_libpl011_rs =3D static_library( + 'pl011', + files('src/lib.rs'), + rust_abi: 'c', + rust_args: rust_args + [ + '--edition', '2021', + ], + dependencies: [ + bilge_dep, + bilge_impl_dep, + qemu_api, + ], +) + +specific_ss.add(when: 'CONFIG_X_PL011_RUST', if_true: [declare_dependency( + link_whole: [_libpl011_rs], +)]) diff --git a/rust/hw/char/pl011/rustfmt.toml b/rust/hw/char/pl011/rustfmt.t= oml new file mode 120000 index 0000000000..39f97b043b --- /dev/null +++ b/rust/hw/char/pl011/rustfmt.toml @@ -0,0 +1 @@ +../rustfmt.toml \ No newline at end of file diff --git a/rust/hw/char/pl011/src/definitions.rs b/rust/hw/char/pl011/src= /definitions.rs new file mode 100644 index 0000000000..66070559d4 --- /dev/null +++ b/rust/hw/char/pl011/src/definitions.rs @@ -0,0 +1,26 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +//! Definitions required by QEMU when registering the device. + +use core::mem::MaybeUninit; + +use qemu_api::bindings::*; + +use crate::device::PL011State; +use qemu_api::definitions::ObjectImpl; + +pub const TYPE_PL011: &std::ffi::CStr =3D c"pl011"; + +#[used] +pub static VMSTATE_PL011: VMStateDescription =3D VMStateDescription { + name: PL011State::TYPE_INFO.name, + unmigratable: true, + ..unsafe { MaybeUninit::::zeroed().assume_init() } +}; + +qemu_api::module_init! { + qom: register_type =3D> { + type_register_static(&PL011State::TYPE_INFO); + } +} diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs new file mode 100644 index 0000000000..150787f70c --- /dev/null +++ b/rust/hw/char/pl011/src/device.rs @@ -0,0 +1,586 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use crate::{ + memory_ops::PL011_OPS, + registers::{self, Interrupt}, + RegisterOffset, +}; +use core::{ + ffi::{c_int, c_uchar, c_uint, c_void, CStr}, + ptr::{addr_of, addr_of_mut, NonNull}, +}; +use qemu_api::bindings::{self, *}; +use qemu_api::definitions::ObjectImpl; + +static PL011_ID_ARM: [c_uchar; 8] =3D [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0,= 0x05, 0xb1]; + +const DATA_BREAK: u32 =3D 1 << 10; + +/// QEMU sourced constant. +pub const PL011_FIFO_DEPTH: usize =3D 16_usize; + +#[repr(C)] +#[derive(Debug)] +/// PL011 Device Model in QEMU +pub struct PL011State { + pub parent_obj: SysBusDevice, + pub iomem: MemoryRegion, + pub readbuff: u32, + #[doc(alias =3D "fr")] + pub flags: registers::Flags, + #[doc(alias =3D "lcr")] + pub line_control: registers::LineControl, + #[doc(alias =3D "rsr")] + pub receive_status_error_clear: registers::ReceiveStatusErrorClear, + #[doc(alias =3D "cr")] + pub control: registers::Control, + pub dmacr: u32, + pub int_enabled: u32, + pub int_level: u32, + pub read_fifo: [u32; PL011_FIFO_DEPTH], + pub ilpr: u32, + pub ibrd: u32, + pub fbrd: u32, + pub ifl: u32, + pub read_pos: usize, + pub read_count: usize, + pub read_trigger: usize, + #[doc(alias =3D "chr")] + pub char_backend: CharBackend, + /// QEMU interrupts + /// + /// ```text + /// * sysbus MMIO region 0: device registers + /// * sysbus IRQ 0: `UARTINTR` (combined interrupt line) + /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line) + /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line) + /// * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line) + /// * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line) + /// * sysbus IRQ 5: `UARTEINTR` (error interrupt line) + /// ``` + #[doc(alias =3D "irq")] + pub interrupts: [qemu_irq; 6usize], + #[doc(alias =3D "clk")] + pub clock: NonNull, + #[doc(alias =3D "migrate_clk")] + pub migrate_clock: bool, +} + +impl ObjectImpl for PL011State { + type Class =3D PL011Class; + const TYPE_INFO: qemu_api::bindings::TypeInfo =3D qemu_api::type_info!= { PL011State }; + const TYPE_NAME: &'static CStr =3D c"pl011"; + const PARENT_TYPE_NAME: Option<&'static CStr> =3D Some(TYPE_SYS_BUS_DE= VICE); + const ABSTRACT: bool =3D false; + const INSTANCE_INIT: Option = =3D Some(pl011_init); + const INSTANCE_POST_INIT: Option =3D None; + const INSTANCE_FINALIZE: Option =3D None; +} + +#[repr(C)] +pub struct PL011Class { + _inner: [u8; 0], +} + +impl qemu_api::definitions::Class for PL011Class { + const CLASS_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), + > =3D Some(crate::device_class::pl011_class_init); + const CLASS_BASE_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut core::ffi= ::c_void), + > =3D None; +} + +#[used] +pub static CLK_NAME: &CStr =3D c"clk"; + +impl PL011State { + pub fn init(&mut self) { + let dev =3D addr_of_mut!(*self).cast::(); + // SAFETY: + // + // self and self.iomem are guaranteed to be valid at this point si= nce callers + // must make sure the `self` reference is valid. + unsafe { + memory_region_init_io( + addr_of_mut!(self.iomem), + addr_of_mut!(*self).cast::(), + &PL011_OPS, + addr_of_mut!(*self).cast::(), + Self::TYPE_INFO.name, + 0x1000, + ); + let sbd =3D addr_of_mut!(*self).cast::(); + sysbus_init_mmio(sbd, addr_of_mut!(self.iomem)); + for irq in self.interrupts.iter_mut() { + sysbus_init_irq(sbd, irq); + } + } + // SAFETY: + // + // self.clock is not initialized at this point; but since `NonNull= <_>` is Copy, we can + // overwrite the undefined value without side effects. This is saf= e since all PL011State + // instances are created by QOM code which calls this function to = initialize the fields; + // therefore no code is able to access an invalid self.clock value. + unsafe { + self.clock =3D NonNull::new(qdev_init_clock_in( + dev, + CLK_NAME.as_ptr(), + None, /* pl011_clock_update */ + addr_of_mut!(*self).cast::(), + ClockEvent_ClockUpdate, + )) + .unwrap(); + } + } + + pub fn read( + &mut self, + offset: hwaddr, + _size: core::ffi::c_uint, + ) -> std::ops::ControlFlow { + use RegisterOffset::*; + + std::ops::ControlFlow::Break(match RegisterOffset::try_from(offset= ) { + Err(v) if (0x3f8..0x400).contains(&v) =3D> { + u64::from(PL011_ID_ARM[((offset - 0xfe0) >> 2) as usize]) + } + Err(_) =3D> { + // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); + 0 + } + Ok(DR) =3D> { + // s->flags &=3D ~PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(false); + let c =3D self.read_fifo[self.read_pos]; + if self.read_count > 0 { + self.read_count -=3D 1; + self.read_pos =3D (self.read_pos + 1) & (self.fifo_dep= th() - 1); + } + if self.read_count =3D=3D 0 { + // self.flags |=3D PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(true); + } + if self.read_count + 1 =3D=3D self.read_trigger { + //self.int_level &=3D ~ INT_RX; + self.int_level &=3D !registers::INT_RX; + } + // Update error bits. + self.receive_status_error_clear =3D c.to_be_bytes()[3].int= o(); + self.update(); + // Must call qemu_chr_fe_accept_input, so return Continue: + return std::ops::ControlFlow::Continue(c.into()); + } + Ok(RSR) =3D> u8::from(self.receive_status_error_clear).into(), + Ok(FR) =3D> u16::from(self.flags).into(), + Ok(FBRD) =3D> self.fbrd.into(), + Ok(ILPR) =3D> self.ilpr.into(), + Ok(IBRD) =3D> self.ibrd.into(), + Ok(LCR_H) =3D> u16::from(self.line_control).into(), + Ok(CR) =3D> { + // We exercise our self-control. + u16::from(self.control).into() + } + Ok(FLS) =3D> self.ifl.into(), + Ok(IMSC) =3D> self.int_enabled.into(), + Ok(RIS) =3D> self.int_level.into(), + Ok(MIS) =3D> u64::from(self.int_level & self.int_enabled), + Ok(ICR) =3D> { + // "The UARTICR Register is the interrupt clear register a= nd is write-only" + // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, = UARTICR + 0 + } + Ok(DMACR) =3D> self.dmacr.into(), + }) + } + + pub fn write(&mut self, offset: hwaddr, value: u64) { + // eprintln!("write offset {offset} value {value}"); + use RegisterOffset::*; + let value: u32 =3D value as u32; + match RegisterOffset::try_from(offset) { + Err(_bad_offset) =3D> { + eprintln!("write bad offset {offset} value {value}"); + } + Ok(DR) =3D> { + // ??? Check if transmitter is enabled. + let ch: u8 =3D value as u8; + // XXX this blocks entire thread. Rewrite to use + // qemu_chr_fe_write and background I/O callbacks + + // SAFETY: self.char_backend is a valid CharBackend instan= ce after it's been + // initialized in realize(). + unsafe { + qemu_chr_fe_write_all(addr_of_mut!(self.char_backend),= &ch, 1); + } + self.loopback_tx(value); + self.int_level |=3D registers::INT_TX; + self.update(); + } + Ok(RSR) =3D> { + self.receive_status_error_clear =3D 0.into(); + } + Ok(FR) =3D> { + // flag writes are ignored + } + Ok(ILPR) =3D> { + self.ilpr =3D value; + } + Ok(IBRD) =3D> { + self.ibrd =3D value; + } + Ok(FBRD) =3D> { + self.fbrd =3D value; + } + Ok(LCR_H) =3D> { + let value =3D value as u16; + let new_val: registers::LineControl =3D value.into(); + // Reset the FIFO state on FIFO enable or disable + if bool::from(self.line_control.fifos_enabled()) + ^ bool::from(new_val.fifos_enabled()) + { + self.reset_fifo(); + } + if self.line_control.send_break() ^ new_val.send_break() { + let mut break_enable: c_int =3D new_val.send_break().i= nto(); + // SAFETY: self.char_backend is a valid CharBackend in= stance after it's been + // initialized in realize(). + unsafe { + qemu_chr_fe_ioctl( + addr_of_mut!(self.char_backend), + CHR_IOCTL_SERIAL_SET_BREAK as i32, + addr_of_mut!(break_enable).cast::(), + ); + } + self.loopback_break(break_enable > 0); + } + self.line_control =3D new_val; + self.set_read_trigger(); + } + Ok(CR) =3D> { + // ??? Need to implement the enable bit. + let value =3D value as u16; + self.control =3D value.into(); + self.loopback_mdmctrl(); + } + Ok(FLS) =3D> { + self.ifl =3D value; + self.set_read_trigger(); + } + Ok(IMSC) =3D> { + self.int_enabled =3D value; + self.update(); + } + Ok(RIS) =3D> {} + Ok(MIS) =3D> {} + Ok(ICR) =3D> { + self.int_level &=3D !value; + self.update(); + } + Ok(DMACR) =3D> { + self.dmacr =3D value; + if value & 3 > 0 { + // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemente= d\n"); + eprintln!("pl011: DMA not implemented"); + } + } + } + } + + #[inline] + fn loopback_tx(&mut self, value: u32) { + if !self.loopback_enabled() { + return; + } + + // Caveat: + // + // In real hardware, TX loopback happens at the serial-bit level + // and then reassembled by the RX logics back into bytes and placed + // into the RX fifo. That is, loopback happens after TX fifo. + // + // Because the real hardware TX fifo is time-drained at the frame + // rate governed by the configured serial format, some loopback + // bytes in TX fifo may still be able to get into the RX fifo + // that could be full at times while being drained at software + // pace. + // + // In such scenario, the RX draining pace is the major factor + // deciding which loopback bytes get into the RX fifo, unless + // hardware flow-control is enabled. + // + // For simplicity, the above described is not emulated. + self.put_fifo(value); + } + + fn loopback_mdmctrl(&mut self) { + if !self.loopback_enabled() { + return; + } + + /* + * Loopback software-driven modem control outputs to modem status = inputs: + * FR.RI <=3D CR.Out2 + * FR.DCD <=3D CR.Out1 + * FR.CTS <=3D CR.RTS + * FR.DSR <=3D CR.DTR + * + * The loopback happens immediately even if this call is triggered + * by setting only CR.LBE. + * + * CTS/RTS updates due to enabled hardware flow controls are not + * dealt with here. + */ + + //fr =3D s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD | + // PL011_FLAG_DSR | PL011_FLAG_CTS); + //fr |=3D (cr & CR_OUT2) ? PL011_FLAG_RI : 0; + //fr |=3D (cr & CR_OUT1) ? PL011_FLAG_DCD : 0; + //fr |=3D (cr & CR_RTS) ? PL011_FLAG_CTS : 0; + //fr |=3D (cr & CR_DTR) ? PL011_FLAG_DSR : 0; + // + self.flags.set_ring_indicator(self.control.out_2()); + self.flags.set_data_carrier_detect(self.control.out_1()); + self.flags.set_clear_to_send(self.control.request_to_send()); + self.flags + .set_data_set_ready(self.control.data_transmit_ready()); + + // Change interrupts based on updated FR + let mut il =3D self.int_level; + + il &=3D !Interrupt::MS; + //il |=3D (fr & PL011_FLAG_DSR) ? INT_DSR : 0; + //il |=3D (fr & PL011_FLAG_DCD) ? INT_DCD : 0; + //il |=3D (fr & PL011_FLAG_CTS) ? INT_CTS : 0; + //il |=3D (fr & PL011_FLAG_RI) ? INT_RI : 0; + + if self.flags.data_set_ready() { + il |=3D Interrupt::DSR as u32; + } + if self.flags.data_carrier_detect() { + il |=3D Interrupt::DCD as u32; + } + if self.flags.clear_to_send() { + il |=3D Interrupt::CTS as u32; + } + if self.flags.ring_indicator() { + il |=3D Interrupt::RI as u32; + } + self.int_level =3D il; + self.update(); + } + + fn loopback_break(&mut self, enable: bool) { + if enable { + self.loopback_tx(DATA_BREAK); + } + } + + fn set_read_trigger(&mut self) { + //#if 0 + // /* The docs say the RX interrupt is triggered when the FIFO = exceeds + // the threshold. However linux only reads the FIFO in resp= onse to an + // interrupt. Triggering the interrupt when the FIFO is non= -empty seems + // to make things work. */ + // if (s->lcr & LCR_FEN) + // s->read_trigger =3D (s->ifl >> 1) & 0x1c; + // else + //#endif + self.read_trigger =3D 1; + } + + pub fn realize(&mut self) { + // SAFETY: self.char_backend has the correct size and alignment fo= r a + // CharBackend object, and its callbacks are of the correct types. + unsafe { + qemu_chr_fe_set_handlers( + addr_of_mut!(self.char_backend), + Some(pl011_can_receive), + Some(pl011_receive), + Some(pl011_event), + None, + addr_of_mut!(*self).cast::(), + core::ptr::null_mut(), + true, + ); + } + } + + pub fn reset(&mut self) { + self.line_control.reset(); + self.receive_status_error_clear.reset(); + self.dmacr =3D 0; + self.int_enabled =3D 0; + self.int_level =3D 0; + self.ilpr =3D 0; + self.ibrd =3D 0; + self.fbrd =3D 0; + self.read_trigger =3D 1; + self.ifl =3D 0x12; + self.control.reset(); + self.flags =3D 0.into(); + self.reset_fifo(); + } + + pub fn reset_fifo(&mut self) { + self.read_count =3D 0; + self.read_pos =3D 0; + + /* Reset FIFO flags */ + self.flags.reset(); + } + + pub fn can_receive(&self) -> bool { + // trace_pl011_can_receive(s->lcr, s->read_count, r); + self.read_count < self.fifo_depth() + } + + pub fn event(&mut self, event: QEMUChrEvent) { + if event =3D=3D bindings::QEMUChrEvent_CHR_EVENT_BREAK && !self.fi= fo_enabled() { + self.put_fifo(DATA_BREAK); + self.receive_status_error_clear.set_break_error(true); + } + } + + #[inline] + pub fn fifo_enabled(&self) -> bool { + matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO) + } + + #[inline] + pub fn loopback_enabled(&self) -> bool { + self.control.enable_loopback() + } + + #[inline] + pub fn fifo_depth(&self) -> usize { + // Note: FIFO depth is expected to be power-of-2 + if self.fifo_enabled() { + return PL011_FIFO_DEPTH; + } + 1 + } + + pub fn put_fifo(&mut self, value: c_uint) { + let depth =3D self.fifo_depth(); + assert!(depth > 0); + let slot =3D (self.read_pos + self.read_count) & (depth - 1); + self.read_fifo[slot] =3D value; + self.read_count +=3D 1; + // s->flags &=3D ~PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(false); + if self.read_count =3D=3D depth { + //s->flags |=3D PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(true); + } + + if self.read_count =3D=3D self.read_trigger { + self.int_level |=3D registers::INT_RX; + self.update(); + } + } + + pub fn update(&mut self) { + let flags =3D self.int_level & self.int_enabled; + for (irq, i) in self.interrupts.iter().zip(IRQMASK) { + // SAFETY: self.interrupts have been initialized in init(). + unsafe { qemu_set_irq(*irq, i32::from(flags & i !=3D 0)) }; + } + } +} + +/// Which bits in the interrupt status matter for each outbound IRQ line ? +pub const IRQMASK: [u32; 6] =3D [ + /* combined IRQ */ + Interrupt::E + | Interrupt::MS + | Interrupt::RT as u32 + | Interrupt::TX as u32 + | Interrupt::RX as u32, + Interrupt::RX as u32, + Interrupt::TX as u32, + Interrupt::RT as u32, + Interrupt::MS, + Interrupt::E, +]; + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int { + assert!(!opaque.is_null()); + let state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_ref().can_receive().into() +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +/// +/// The buffer and size arguments must also be valid. +#[no_mangle] +pub unsafe extern "C" fn pl011_receive( + opaque: *mut core::ffi::c_void, + buf: *const u8, + size: core::ffi::c_int, +) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + if state.as_ref().loopback_enabled() { + return; + } + if size > 0 { + assert!(!buf.is_null()); + state.as_mut().put_fifo(*buf.cast::()) + } +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_event(opaque: *mut core::ffi::c_void, event= : QEMUChrEvent) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().event(event) +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer for `c= hr`. +#[no_mangle] +pub unsafe extern "C" fn pl011_create( + addr: u64, + irq: qemu_irq, + chr: *mut Chardev, +) -> *mut DeviceState { + let dev: *mut DeviceState =3D unsafe { qdev_new(PL011State::TYPE_INFO.= name) }; + assert!(!dev.is_null()); + let sysbus: *mut SysBusDevice =3D dev as *mut SysBusDevice; + + qdev_prop_set_chr(dev, bindings::TYPE_CHARDEV.as_ptr(), chr); + sysbus_realize_and_unref(sysbus, addr_of!(error_fatal) as *mut *mut Er= ror); + sysbus_mmio_map(sysbus, 0, addr); + sysbus_connect_irq(sysbus, 0, irq); + dev +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_init(obj: *mut Object) { + assert!(!obj.is_null()); + let mut state =3D NonNull::new_unchecked(obj.cast::()); + state.as_mut().init(); +} diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr= c/device_class.rs new file mode 100644 index 0000000000..6b99239133 --- /dev/null +++ b/rust/hw/char/pl011/src/device_class.rs @@ -0,0 +1,58 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use core::ptr::NonNull; + +use qemu_api::bindings::*; + +use crate::{definitions::VMSTATE_PL011, device::PL011State}; + +qemu_api::declare_properties! { + PL011_PROPERTIES, + qemu_api::define_property!( + c"chardev", + PL011State, + char_backend, + unsafe { &qdev_prop_chr }, + CharBackend + ), + qemu_api::define_property!( + c"migrate-clk", + PL011State, + migrate_clock, + unsafe { &qdev_prop_bool }, + bool + ), +} + +qemu_api::device_class_init! { + pl011_class_init, + props =3D> PL011_PROPERTIES, + realize_fn =3D> Some(pl011_realize), + reset_fn =3D> Some(pl011_reset), + vmsd =3D> VMSTATE_PL011, +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_realize(dev: *mut DeviceState, _errp: *mut = *mut Error) { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().realize(); +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer, that = has +/// the same size as [`PL011State`]. We also expect the device is +/// readable/writeable from one thread at any time. +#[no_mangle] +pub unsafe extern "C" fn pl011_reset(dev: *mut DeviceState) { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().reset(); +} diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs new file mode 100644 index 0000000000..697d2ef5a6 --- /dev/null +++ b/rust/hw/char/pl011/src/lib.rs @@ -0,0 +1,584 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later +// +// PL011 QEMU Device Model +// +// This library implements a device model for the PrimeCell=C2=AE UART (PL= 011) +// device in QEMU. +// +#![doc =3D include_str!("../README.md")] +//! # Library crate +//! +//! See [`PL011State`](crate::device::PL011State) for the device model typ= e and +//! the [`registers`] module for register types. + +#![deny( + rustdoc::broken_intra_doc_links, + rustdoc::redundant_explicit_links, + clippy::correctness, + clippy::suspicious, + clippy::complexity, + clippy::perf, + clippy::cargo, + clippy::nursery, + clippy::style, + // restriction group + clippy::dbg_macro, + clippy::as_underscore, + clippy::assertions_on_result_states, + // pedantic group + clippy::doc_markdown, + clippy::borrow_as_ptr, + clippy::cast_lossless, + clippy::option_if_let_else, + clippy::missing_const_for_fn, + clippy::cognitive_complexity, + clippy::missing_safety_doc, + )] + +extern crate bilge; +extern crate bilge_impl; +extern crate qemu_api; + +pub mod definitions; +pub mod device; +pub mod device_class; +pub mod memory_ops; + +/// Offset of each register from the base memory address of the device. +/// +/// # Source +/// ARM DDI 0183G, Table 3-1 p.3-3 +#[doc(alias =3D "offset")] +#[allow(non_camel_case_types)] +#[repr(u64)] +#[derive(Debug)] +pub enum RegisterOffset { + /// Data Register + /// + /// A write to this register initiates the actual data transmission + #[doc(alias =3D "UARTDR")] + DR =3D 0x000, + /// Receive Status Register or Error Clear Register + #[doc(alias =3D "UARTRSR")] + #[doc(alias =3D "UARTECR")] + RSR =3D 0x004, + /// Flag Register + /// + /// A read of this register shows if transmission is complete + #[doc(alias =3D "UARTFR")] + FR =3D 0x018, + /// Fractional Baud Rate Register + /// + /// responsible for baud rate speed + #[doc(alias =3D "UARTFBRD")] + FBRD =3D 0x028, + /// `IrDA` Low-Power Counter Register + #[doc(alias =3D "UARTILPR")] + ILPR =3D 0x020, + /// Integer Baud Rate Register + /// + /// Responsible for baud rate speed + #[doc(alias =3D "UARTIBRD")] + IBRD =3D 0x024, + /// line control register (data frame format) + #[doc(alias =3D "UARTLCR_H")] + LCR_H =3D 0x02C, + /// Toggle UART, transmission or reception + #[doc(alias =3D "UARTCR")] + CR =3D 0x030, + /// Interrupt FIFO Level Select Register + #[doc(alias =3D "UARTIFLS")] + FLS =3D 0x034, + /// Interrupt Mask Set/Clear Register + #[doc(alias =3D "UARTIMSC")] + IMSC =3D 0x038, + /// Raw Interrupt Status Register + #[doc(alias =3D "UARTRIS")] + RIS =3D 0x03C, + /// Masked Interrupt Status Register + #[doc(alias =3D "UARTMIS")] + MIS =3D 0x040, + /// Interrupt Clear Register + #[doc(alias =3D "UARTICR")] + ICR =3D 0x044, + /// DMA control Register + #[doc(alias =3D "UARTDMACR")] + DMACR =3D 0x048, + ///// Reserved, offsets `0x04C` to `0x07C`. + //Reserved =3D 0x04C, +} + +impl core::convert::TryFrom for RegisterOffset { + type Error =3D u64; + + fn try_from(value: u64) -> Result { + macro_rules! case { + ($($discriminant:ident),*$(,)*) =3D> { + /* check that matching on all macro arguments compiles, wh= ich means we are not + * missing any enum value; if the type definition ever cha= nges this will stop + * compiling. + */ + const fn _assert_exhaustive(val: RegisterOffset) { + match val { + $(RegisterOffset::$discriminant =3D> (),)* + } + } + + match value { + $(x if x =3D=3D Self::$discriminant as u64 =3D> Ok(Sel= f::$discriminant),)* + _ =3D> Err(value), + } + } + } + case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, = MIS, ICR, DMACR } + } +} + +pub mod registers { + //! Device registers exposed as typed structs which are backed by arbi= trary + //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. + //! + //! All PL011 registers are essentially 32-bit wide, but are typed her= e as + //! bitmaps with only the necessary width. That is, if a struct bitmap + //! in this module is for example 16 bits long, it should be conceived + //! as a 32-bit register where the unmentioned higher bits are always + //! unused thus treated as zero when read or written. + use bilge::prelude::*; + + // TODO: FIFO Mode has different semantics + /// Data Register, `UARTDR` + /// + /// The `UARTDR` register is the data register. + /// + /// For words to be transmitted: + /// + /// - if the FIFOs are enabled, data written to this location is pushe= d onto + /// the transmit + /// FIFO + /// - if the FIFOs are not enabled, data is stored in the transmitter + /// holding register (the + /// bottom word of the transmit FIFO). + /// + /// The write operation initiates transmission from the UART. The data= is + /// prefixed with a start bit, appended with the appropriate parity bit + /// (if parity is enabled), and a stop bit. The resultant word is then + /// transmitted. + /// + /// For received words: + /// + /// - if the FIFOs are enabled, the data byte and the 4-bit status (br= eak, + /// frame, parity, + /// and overrun) is pushed onto the 12-bit wide receive FIFO + /// - if the FIFOs are not enabled, the data byte and status are store= d in + /// the receiving + /// holding register (the bottom word of the receive FIFO). + /// + /// The received data byte is read by performing reads from the `UARTD= R` + /// register along with the corresponding status information. The stat= us + /// information can also be read by a read of the `UARTRSR/UARTECR` + /// register. + /// + /// # Note + /// + /// You must disable the UART before any of the control registers are + /// reprogrammed. When the UART is disabled in the middle of + /// transmission or reception, it completes the current character befo= re + /// stopping. + /// + /// # Source + /// ARM DDI 0183G 3.3.1 Data Register, UARTDR + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + #[doc(alias =3D "UARTDR")] + pub struct Data { + _reserved: u4, + pub data: u8, + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + } + + // TODO: FIFO Mode has different semantics + /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` + /// + /// The UARTRSR/UARTECR register is the receive status register/error = clear + /// register. Receive status can also be read from the `UARTRSR` + /// register. If the status is read from this register, then the status + /// information for break, framing and parity corresponds to the + /// data character read from the [Data register](Data), `UARTDR` prior= to + /// reading the UARTRSR register. The status information for overrun is + /// set immediately when an overrun condition occurs. + /// + /// + /// # Note + /// The received data character must be read first from the [Data + /// Register](Data), `UARTDR` before reading the error status associat= ed + /// with that data character from the `UARTRSR` register. This read + /// sequence cannot be reversed, because the `UARTRSR` register is + /// updated only when a read occurs from the `UARTDR` register. Howeve= r, + /// the status information can also be obtained by reading the `UARTDR` + /// register + /// + /// # Source + /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, + /// UARTRSR/UARTECR + #[bitsize(8)] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct ReceiveStatusErrorClear { + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + _reserved_unpredictable: u4, + } + + impl ReceiveStatusErrorClear { + pub fn reset(&mut self) { + // All the bits are cleared to 0 on reset. + *self =3D 0.into(); + } + } + + impl Default for ReceiveStatusErrorClear { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Flag Register, `UARTFR` + #[doc(alias =3D "UARTFR")] + pub struct Flags { + /// CTS Clear to send. This bit is the complement of the UART clea= r to + /// send, `nUARTCTS`, modem status input. That is, the bit is 1 + /// when `nUARTCTS` is LOW. + pub clear_to_send: bool, + /// DSR Data set ready. This bit is the complement of the UART dat= a set + /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 w= hen + /// `nUARTDSR` is LOW. + pub data_set_ready: bool, + /// DCD Data carrier detect. This bit is the complement of the UAR= T data + /// carrier detect, `nUARTDCD`, modem status input. That is, the b= it is + /// 1 when `nUARTDCD` is LOW. + pub data_carrier_detect: bool, + /// BUSY UART busy. If this bit is set to 1, the UART is busy + /// transmitting data. This bit remains set until the complete + /// byte, including all the stop bits, has been sent from the + /// shift register. This bit is set as soon as the transmit FIFO + /// becomes non-empty, regardless of whether the UART is enabled + /// or not. + pub busy: bool, + /// RXFE Receive FIFO empty. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the receive holding + /// register is empty. If the FIFO is enabled, the RXFE bit is + /// set when the receive FIFO is empty. + pub receive_fifo_empty: bool, + /// TXFF Transmit FIFO full. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the transmit holding + /// register is full. If the FIFO is enabled, the TXFF bit is + /// set when the transmit FIFO is full. + pub transmit_fifo_full: bool, + /// RXFF Receive FIFO full. The meaning of this bit depends on the= state + /// of the FEN bit in the UARTLCR_H register. If the FIFO is + /// disabled, this bit is set when the receive holding register + /// is full. If the FIFO is enabled, the RXFF bit is set when + /// the receive FIFO is full. + pub receive_fifo_full: bool, + /// Transmit FIFO empty. The meaning of this bit depends on the st= ate of + /// the FEN bit in the [Line Control register](LineControl), + /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the + /// transmit holding register is empty. If the FIFO is enabled, + /// the TXFE bit is set when the transmit FIFO is empty. This + /// bit does not indicate if there is data in the transmit shift + /// register. + pub transmit_fifo_empty: bool, + /// `RI`, is `true` when `nUARTRI` is `LOW`. + pub ring_indicator: bool, + _reserved_zero_no_modify: u7, + } + + impl Flags { + pub fn reset(&mut self) { + // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE a= re 1 + self.set_receive_fifo_full(false); + self.set_transmit_fifo_full(false); + self.set_busy(false); + self.set_receive_fifo_empty(true); + self.set_transmit_fifo_empty(true); + } + } + + impl Default for Flags { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Line Control Register, `UARTLCR_H` + #[doc(alias =3D "UARTLCR_H")] + pub struct LineControl { + /// 15:8 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u8, + /// 7 SPS Stick parity select. + /// 0 =3D stick parity is disabled + /// 1 =3D either: + /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt= ed and checked + /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is + /// transmitted and checked as a 0. This bit has no effect when + /// the PEN bit disables parity checking and generation. See Table= 3-11 + /// on page 3-14 for the parity truth table. + pub sticky_parity: bool, + /// WLEN Word length. These bits indicate the number of data bits + /// transmitted or received in a frame as follows: b11 =3D 8 bits + /// b10 =3D 7 bits + /// b01 =3D 6 bits + /// b00 =3D 5 bits. + pub word_length: WordLength, + /// FEN Enable FIFOs: + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO + /// buffers are enabled (FIFO mode). + pub fifos_enabled: Mode, + /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop= bits + /// are transmitted at the end of the frame. The receive + /// logic does not check for two stop bits being received. + pub two_stops_bits: bool, + /// EPS Even parity select. Controls the type of parity the UART u= ses + /// during transmission and reception: + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + /// This bit has no effect when the `PEN` bit disables parity chec= king + /// and generation. See Table 3-11 on page 3-14 for the parity + /// truth table. + pub parity: Parity, + /// 1 PEN Parity enable: + /// + /// - 0 =3D parity is disabled and no parity bit added to the data= frame + /// - 1 =3D parity checking and generation is enabled. + /// + /// See Table 3-11 on page 3-14 for the parity truth table. + pub parity_enabled: bool, + /// BRK Send break. + /// + /// If this bit is set to `1`, a low-level is continually output o= n the + /// `UARTTXD` output, after completing transmission of the + /// current character. For the proper execution of the break comma= nd, + /// the software must set this bit for at least two complete + /// frames. For normal use, this bit must be cleared to `0`. + pub send_break: bool, + } + + impl LineControl { + pub fn reset(&mut self) { + // All the bits are cleared to 0 when reset. + *self =3D 0.into(); + } + } + + impl Default for LineControl { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `EPS` "Even parity select", field of [Line Control + /// register](LineControl). + pub enum Parity { + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + Odd =3D 0, + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + Even =3D 1, + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control + /// register](LineControl). + pub enum Mode { + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers + Character =3D 0, + /// 1 =3D transmit and receive FIFO buffers are enabled (FIFO mode= ). + FIFO =3D 1, + } + + impl From for bool { + fn from(val: Mode) -> Self { + matches!(val, Mode::FIFO) + } + } + + #[bitsize(2)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `WLEN` Word length, field of [Line Control register](LineControl). + /// + /// These bits indicate the number of data bits transmitted or receive= d in a + /// frame as follows: + pub enum WordLength { + /// b11 =3D 8 bits + _8Bits =3D 0b11, + /// b10 =3D 7 bits + _7Bits =3D 0b10, + /// b01 =3D 6 bits + _6Bits =3D 0b01, + /// b00 =3D 5 bits. + _5Bits =3D 0b00, + } + + /// Control Register, `UARTCR` + /// + /// The `UARTCR` register is the control register. All the bits are cl= eared + /// to `0` on reset except for bits `9` and `8` that are set to `1`. + /// + /// # Source + /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 + #[bitsize(16)] + #[doc(alias =3D "UARTCR")] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct Control { + /// `UARTEN` UART enable: 0 =3D UART is disabled. If the UART is d= isabled + /// in the middle of transmission or reception, it completes the c= urrent + /// character before stopping. 1 =3D the UART is enabled. Data + /// transmission and reception occurs for either UART signals or S= IR + /// signals depending on the setting of the SIREN bit. + pub enable_uart: bool, + /// `SIREN` `SIR` enable: 0 =3D IrDA SIR ENDEC is disabled. `nSIRO= UT` + /// remains LOW (no light pulse generated), and signal transitions= on + /// SIRIN have no effect. 1 =3D IrDA SIR ENDEC is enabled. Data is + /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains= HIGH, + /// in the marking state. Signal transitions on UARTRXD or modem s= tatus + /// inputs have no effect. This bit has no effect if the UARTEN bit + /// disables the UART. + pub enable_sir: bool, + /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA enc= oding + /// mode. If this bit is cleared to 0, low-level bits are transmit= ted as + /// an active high pulse with a width of 3/ 16th of the bit period= . If + /// this bit is set to 1, low-level bits are transmitted with a pu= lse + /// width that is 3 times the period of the IrLPBaud16 input signa= l, + /// regardless of the selected bit rate. Setting this bit uses less + /// power, but might reduce transmission distances. + pub sir_lowpower_irda_mode: u1, + /// Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u4, + /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN b= it is + /// set to 1 and the SIRTEST bit in the Test Control register, UAR= TTCR + /// on page 4-5 is set to 1, then the nSIROUT path is inverted, an= d fed + /// through to the SIRIN path. The SIRTEST bit in the test registe= r must + /// be set to 1 to override the normal half-duplex SIR operation. = This + /// must be the requirement for accessing the test registers during + /// normal operation, and SIRTEST must be cleared to 0 when loopba= ck + /// testing is finished. This feature reduces the amount of extern= al + /// coupling required during system test. If this bit is set to 1,= and + /// the SIRTEST bit is set to 0, the UARTTXD path is fed through t= o the + /// UARTRXD path. In either SIR mode or UART mode, when this bit i= s set, + /// the modem outputs are also fed through to the modem inputs. Th= is bit + /// is cleared to 0 on reset, to disable loopback. + pub enable_loopback: bool, + /// `TXE` Transmit enable. If this bit is set to 1, the transmit s= ection + /// of the UART is enabled. Data transmission occurs for either UA= RT + /// signals, or SIR signals depending on the setting of the SIREN = bit. + /// When the UART is disabled in the middle of transmission, it + /// completes the current character before stopping. + pub enable_transmit: bool, + /// `RXE` Receive enable. If this bit is set to 1, the receive sec= tion + /// of the UART is enabled. Data reception occurs for either UART + /// signals or SIR signals depending on the setting of the SIREN b= it. + /// When the UART is disabled in the middle of reception, it compl= etes + /// the current character before stopping. + pub enable_receive: bool, + /// `DTR` Data transmit ready. This bit is the complement of the U= ART + /// data transmit ready, `nUARTDTR`, modem status output. That is,= when + /// the bit is programmed to a 1 then `nUARTDTR` is LOW. + pub data_transmit_ready: bool, + /// `RTS` Request to send. This bit is the complement of the UART + /// request to send, `nUARTRTS`, modem status output. That is, whe= n the + /// bit is programmed to a 1 then `nUARTRTS` is LOW. + pub request_to_send: bool, + /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1= `) + /// modem status output. That is, when the bit is programmed to a = 1 the + /// output is 0. For DTE this can be used as Data Carrier Detect (= DCD). + pub out_1: bool, + /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2= `) + /// modem status output. That is, when the bit is programmed to a = 1, the + /// output is 0. For DTE this can be used as Ring Indicator (RI). + pub out_2: bool, + /// `RTSEn` RTS hardware flow control enable. If this bit is set t= o 1, + /// RTS hardware flow control is enabled. Data is only requested w= hen + /// there is space in the receive FIFO for it to be received. + pub rts_hardware_flow_control_enable: bool, + /// `CTSEn` CTS hardware flow control enable. If this bit is set t= o 1, + /// CTS hardware flow control is enabled. Data is only transmitted= when + /// the `nUARTCTS` signal is asserted. + pub cts_hardware_flow_control_enable: bool, + } + + impl Control { + pub fn reset(&mut self) { + *self =3D 0.into(); + self.set_enable_receive(true); + self.set_enable_transmit(true); + } + } + + impl Default for Control { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC + pub const INT_OE: u32 =3D 1 << 10; + pub const INT_BE: u32 =3D 1 << 9; + pub const INT_PE: u32 =3D 1 << 8; + pub const INT_FE: u32 =3D 1 << 7; + pub const INT_RT: u32 =3D 1 << 6; + pub const INT_TX: u32 =3D 1 << 5; + pub const INT_RX: u32 =3D 1 << 4; + pub const INT_DSR: u32 =3D 1 << 3; + pub const INT_DCD: u32 =3D 1 << 2; + pub const INT_CTS: u32 =3D 1 << 1; + pub const INT_RI: u32 =3D 1 << 0; + pub const INT_E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const INT_MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + + #[repr(u32)] + pub enum Interrupt { + OE =3D 1 << 10, + BE =3D 1 << 9, + PE =3D 1 << 8, + FE =3D 1 << 7, + RT =3D 1 << 6, + TX =3D 1 << 5, + RX =3D 1 << 4, + DSR =3D 1 << 3, + DCD =3D 1 << 2, + CTS =3D 1 << 1, + RI =3D 1 << 0, + } + + impl Interrupt { + pub const E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + } +} + +// TODO: You must disable the UART before any of the control registers are +// reprogrammed. When the UART is disabled in the middle of transmission or +// reception, it completes the current character before stopping diff --git a/rust/hw/char/pl011/src/memory_ops.rs b/rust/hw/char/pl011/src/= memory_ops.rs new file mode 100644 index 0000000000..5e185b7cd7 --- /dev/null +++ b/rust/hw/char/pl011/src/memory_ops.rs @@ -0,0 +1,56 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use core::{mem::MaybeUninit, ptr::NonNull}; + +use qemu_api::bindings::*; + +use crate::device::PL011State; + +pub static PL011_OPS: MemoryRegionOps =3D MemoryRegionOps { + read: Some(pl011_read), + write: Some(pl011_write), + read_with_attrs: None, + write_with_attrs: None, + endianness: device_endian_DEVICE_NATIVE_ENDIAN, + valid: unsafe { MaybeUninit::::zeroed()= .assume_init() }, + impl_: MemoryRegionOps__bindgen_ty_2 { + min_access_size: 4, + max_access_size: 4, + ..unsafe { MaybeUninit::::zeroed().= assume_init() } + }, +}; + +#[no_mangle] +unsafe extern "C" fn pl011_read( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + size: core::ffi::c_uint, +) -> u64 { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + let val =3D state.as_mut().read(addr, size); + match val { + std::ops::ControlFlow::Break(val) =3D> val, + std::ops::ControlFlow::Continue(val) =3D> { + // SAFETY: self.char_backend is a valid CharBackend instance a= fter it's been + // initialized in realize(). + let cb_ptr =3D core::ptr::addr_of_mut!(state.as_mut().char_bac= kend); + unsafe { qemu_chr_fe_accept_input(cb_ptr) }; + + val + } + } +} + +#[no_mangle] +unsafe extern "C" fn pl011_write( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + data: u64, + _size: core::ffi::c_uint, +) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().write(addr, data) +} diff --git a/rust/hw/meson.build b/rust/hw/meson.build new file mode 100644 index 0000000000..860196645e --- /dev/null +++ b/rust/hw/meson.build @@ -0,0 +1 @@ +subdir('char') diff --git a/rust/meson.build b/rust/meson.build index a903c7c602..4c858e9d1f 100644 --- a/rust/meson.build +++ b/rust/meson.build @@ -11,3 +11,5 @@ _lib_bindings_rs =3D static_library( ) =20 subdir('qemu-api') + +subdir('hw') diff --git a/subprojects/.gitignore b/subprojects/.gitignore index adca0266be..50f173f90d 100644 --- a/subprojects/.gitignore +++ b/subprojects/.gitignore @@ -6,3 +6,14 @@ /keycodemapdb /libvfio-user /slirp +/arbitrary-int-1.2.7 +/bilge-0.2.0 +/bilge-impl-0.2.0 +/either-1.12.0 +/itertools-0.11.0 +/proc-macro-error-1.0.4 +/proc-macro-error-attr-1.0.4 +/proc-macro2-1.0.84 +/quote-1.0.36 +/syn-2.0.66 +/unicode-ident-1.0.12 diff --git a/subprojects/arbitrary-int.wrap b/subprojects/arbitrary-int.wrap new file mode 100644 index 0000000000..d8535bdc1e --- /dev/null +++ b/subprojects/arbitrary-int.wrap @@ -0,0 +1,9 @@ +[wrap-file] +directory =3D arbitrary-int-1.2.7 +source_url =3D https://crates.io/api/v1/crates/arbitrary-int/1.2.7/download +source_filename =3D arbitrary-int-1.2.7.tar.gz +source_hash =3D c84fc003e338a6f69fbd4f7fe9f92b535ff13e9af8997f3b14b6ddff8b= 1df46d +patch_directory =3D arbitrary-int + +[provide] +dependency_names =3D arbitrary_int_dep diff --git a/subprojects/bilge-impl.wrap b/subprojects/bilge-impl.wrap new file mode 100644 index 0000000000..f0d0c22fc9 --- /dev/null +++ b/subprojects/bilge-impl.wrap @@ -0,0 +1,10 @@ +[wrap-file] +directory =3D bilge-impl-0.2.0 +source_url =3D https://crates.io/api/v1/crates/bilge-impl/0.2.0/download +source_filename =3D bilge-impl-0.2.0.tar.gz +source_hash =3D feb11e002038ad243af39c2068c8a72bcf147acf05025dcdb916fcc000= adb2d8 +#method =3D cargo +patch_directory =3D bilge-impl + +[provide] +dependency_names =3D bilge_impl_dep diff --git a/subprojects/bilge.wrap b/subprojects/bilge.wrap new file mode 100644 index 0000000000..a37638e356 --- /dev/null +++ b/subprojects/bilge.wrap @@ -0,0 +1,10 @@ +[wrap-file] +directory =3D bilge-0.2.0 +source_url =3D https://crates.io/api/v1/crates/bilge/0.2.0/download +source_filename =3D bilge-0.2.0.tar.gz +source_hash =3D dc707ed8ebf81de5cd6c7f48f54b4c8621760926cdf35a57000747c512= e67b57 +#method =3D cargo +patch_directory =3D bilge + +[provide] +dependency_names =3D bilge-0.2.0-rs diff --git a/subprojects/either.wrap b/subprojects/either.wrap new file mode 100644 index 0000000000..df2f09a986 --- /dev/null +++ b/subprojects/either.wrap @@ -0,0 +1,10 @@ +[wrap-file] +directory =3D either-1.12.0 +source_url =3D https://crates.io/api/v1/crates/either/1.12.0/download +source_filename =3D either-1.12.0.tar.gz +source_hash =3D 3dca9240753cf90908d7e4aac30f630662b02aebaa1b58a3cadabdb233= 85b58b +#method =3D cargo +patch_directory =3D either + +[provide] +dependency_names =3D either_dep diff --git a/subprojects/itertools.wrap b/subprojects/itertools.wrap new file mode 100644 index 0000000000..93961e00ab --- /dev/null +++ b/subprojects/itertools.wrap @@ -0,0 +1,10 @@ +[wrap-file] +directory =3D itertools-0.11.0 +source_url =3D https://crates.io/api/v1/crates/itertools/0.11.0/download +source_filename =3D itertools-0.11.0.tar.gz +source_hash =3D b1c173a5686ce8bfa551b3563d0c2170bf24ca44da99c7ca4bfdab5418= c3fe57 +#method =3D cargo +patch_directory =3D itertools + +[provide] +dependency_names =3D itertools_dep diff --git a/subprojects/packagefiles/arbitrary-int/meson.build b/subprojec= ts/packagefiles/arbitrary-int/meson.build new file mode 100644 index 0000000000..6ce8eac79a --- /dev/null +++ b/subprojects/packagefiles/arbitrary-int/meson.build @@ -0,0 +1,19 @@ +project('arbitrary-int', 'rust', + version: '1.2.7', + license: 'GPL-2.0-or-later', + default_options: []) + +_arbitrary_int_rs =3D static_library( + 'arbitrary_int', + files('src/lib.rs'), + gnu_symbol_visibility: 'hidden', + rust_abi: 'rust', + rust_args: [ + '--edition', '2021', + ], + dependencies: [], +) + +arbitrary_int_dep =3D declare_dependency( + link_with: _arbitrary_int_rs, +) diff --git a/subprojects/packagefiles/bilge-impl/meson.build b/subprojects/= packagefiles/bilge-impl/meson.build new file mode 100644 index 0000000000..6413afaa4d --- /dev/null +++ b/subprojects/packagefiles/bilge-impl/meson.build @@ -0,0 +1,36 @@ +project('bilge-impl', 'rust', + version: '0.2.0', + license: 'GPL-2.0-or-later', + default_options: []) + +itertools_dep =3D subproject('itertools').get_variable('itertools_dep') +proc_macro_error_attr_dep =3D subproject('proc-macro-error-attr').get_vari= able('proc_macro_error_attr_dep') +proc_macro_error_dep =3D subproject('proc-macro-error').get_variable('proc= _macro_error_dep') +quote_dep =3D subproject('quote').get_variable('quote_dep') +syn_dep =3D subproject('syn').get_variable('syn_dep') +proc_macro2_dep =3D subproject('proc-macro2').get_variable('proc_macro2_de= p') + +rust =3D import('rust') + +_bilge_impl_rs =3D rust.proc_macro( + 'bilge_impl', + files('src/lib.rs'), + rust_args: [ + '--edition', '2021', + '--cfg', 'use_fallback', + '--cfg', 'feature=3D"syn-error"', + '--cfg', 'feature=3D"proc-macro"', + ], + dependencies: [ + itertools_dep, + proc_macro_error_attr_dep, + proc_macro_error_dep, + quote_dep, + syn_dep, + proc_macro2_dep, + ], +) + +bilge_impl_dep =3D declare_dependency( + link_with: _bilge_impl_rs, +) diff --git a/subprojects/packagefiles/bilge/meson.build b/subprojects/packa= gefiles/bilge/meson.build new file mode 100644 index 0000000000..05d257da61 --- /dev/null +++ b/subprojects/packagefiles/bilge/meson.build @@ -0,0 +1,25 @@ +project( + 'bilge', + 'rust', + version : '0.2.0', + license : 'MIT or Apache-2.0', +) + +arbitrary_int_dep =3D subproject('arbitrary-int').get_variable('arbitrary_= int_dep') +bilge_impl_dep =3D subproject('bilge-impl').get_variable('bilge_impl_dep') + +lib =3D static_library( + 'bilge', + 'src/lib.rs', + override_options : ['rust_std=3D2021', 'build.rust_std=3D2021'], + rust_abi : 'rust', + native : true, + dependencies: [ + arbitrary_int_dep, + bilge_impl_dep, + ], +) + +bilge_dep =3D declare_dependency( + link_with : [lib], +) diff --git a/subprojects/packagefiles/either/meson.build b/subprojects/pack= agefiles/either/meson.build new file mode 100644 index 0000000000..e6ab0e849b --- /dev/null +++ b/subprojects/packagefiles/either/meson.build @@ -0,0 +1,21 @@ +project('either', 'rust', + version: '1.12.0', + license: 'GPL-2.0-or-later', + default_options: []) + +_either_rs =3D static_library( + 'either', + files('src/lib.rs'), + gnu_symbol_visibility: 'hidden', + rust_abi: 'rust', + rust_args: [ + '--edition', '2018', + '--cfg', 'feature=3D"use_std"', + '--cfg', 'feature=3D"use_alloc"', + ], + dependencies: [], +) + +either_dep =3D declare_dependency( + link_with: _either_rs, +) diff --git a/subprojects/packagefiles/itertools/meson.build b/subprojects/p= ackagefiles/itertools/meson.build new file mode 100644 index 0000000000..d897a615f0 --- /dev/null +++ b/subprojects/packagefiles/itertools/meson.build @@ -0,0 +1,25 @@ +project('itertools', 'rust', + version: '0.11.0', + license: 'GPL-2.0-or-later', + default_options: []) + +either_dep =3D subproject('either').get_variable('either_dep') + +_itertools_rs =3D static_library( + 'itertools', + files('src/lib.rs'), + gnu_symbol_visibility: 'hidden', + rust_abi: 'rust', + rust_args: [ + '--edition', '2018', + '--cfg', 'feature=3D"use_std"', + '--cfg', 'feature=3D"use_alloc"', + ], + dependencies: [ + either_dep, + ], +) + +itertools_dep =3D declare_dependency( + link_with: _itertools_rs, +) diff --git a/subprojects/packagefiles/proc-macro-error-attr/meson.build b/s= ubprojects/packagefiles/proc-macro-error-attr/meson.build new file mode 100644 index 0000000000..ed0f05e9e6 --- /dev/null +++ b/subprojects/packagefiles/proc-macro-error-attr/meson.build @@ -0,0 +1,27 @@ +project('proc-macro-error-attr', 'rust', + version: '1.12.0', + license: 'GPL-2.0-or-later', + default_options: []) + +proc_macro2_dep =3D subproject('proc-macro2').get_variable('proc_macro2_de= p') +quote_dep =3D subproject('quote').get_variable('quote_dep') + +rust =3D import('rust') +_proc_macro_error_attr_rs =3D rust.proc_macro( + 'proc_macro_error_attr', + files('src/lib.rs'), + rust_args: [ + '--edition', '2018', + '--cfg', 'use_fallback', + '--cfg', 'feature=3D"syn-error"', + '--cfg', 'feature=3D"proc-macro"' + ], + dependencies: [ + proc_macro2_dep, + quote_dep, + ], +) + +proc_macro_error_attr_dep =3D declare_dependency( + link_with: _proc_macro_error_attr_rs, +) diff --git a/subprojects/packagefiles/proc-macro-error/meson.build b/subpro= jects/packagefiles/proc-macro-error/meson.build new file mode 100644 index 0000000000..4c9e4f70ef --- /dev/null +++ b/subprojects/packagefiles/proc-macro-error/meson.build @@ -0,0 +1,32 @@ +project('proc-macro-error', 'rust', + version: '1.0.4', + license: 'GPL-2.0-or-later', + default_options: []) + +proc_macro_error_attr_dep =3D subproject('proc-macro-error-attr').get_vari= able('proc_macro_error_attr_dep') +proc_macro2_dep =3D subproject('proc-macro2').get_variable('proc_macro2_de= p') +quote_dep =3D subproject('quote').get_variable('quote_dep') +syn_dep =3D subproject('syn').get_variable('syn_dep') + +_proc_macro_error_rs =3D static_library( + 'proc_macro_error', + files('src/lib.rs'), + rust_abi: 'rust', + rust_args: [ + '--edition', '2018', + '--cfg', 'use_fallback', + '--cfg', 'feature=3D"syn-error"', + '--cfg', 'feature=3D"proc-macro"', + '-A', 'non_fmt_panics' + ], + dependencies: [ + proc_macro_error_attr_dep, + proc_macro2_dep, + quote_dep, + syn_dep, + ], +) + +proc_macro_error_dep =3D declare_dependency( + link_with: _proc_macro_error_rs, +) diff --git a/subprojects/packagefiles/proc-macro2/meson.build b/subprojects= /packagefiles/proc-macro2/meson.build new file mode 100644 index 0000000000..9efb441b7a --- /dev/null +++ b/subprojects/packagefiles/proc-macro2/meson.build @@ -0,0 +1,26 @@ +project('proc-macro2', 'rust', + version: '1.0.84', + license: 'GPL-2.0-or-later', + default_options: []) + +unicode_ident_dep =3D subproject('unicode-ident').get_variable('unicode_id= ent_dep') + +_proc_macro2_rs =3D static_library( + 'proc_macro2', + files('src/lib.rs'), + gnu_symbol_visibility: 'hidden', + rust_abi: 'rust', + rust_args: [ + '--edition', '2021', + '--cfg', 'feature=3D"proc-macro"', + '--cfg', 'span_locations', + '--cfg', 'wrap_proc_macro', + ], + dependencies: [ + unicode_ident_dep, + ], +) + +proc_macro2_dep =3D declare_dependency( + link_with: _proc_macro2_rs, +) diff --git a/subprojects/packagefiles/quote/meson.build b/subprojects/packa= gefiles/quote/meson.build new file mode 100644 index 0000000000..4570e93b19 --- /dev/null +++ b/subprojects/packagefiles/quote/meson.build @@ -0,0 +1,25 @@ +project('quote', 'rust', + version: '1.12.0', + license: 'GPL-2.0-or-later', + default_options: []) + +proc_macro2_dep =3D subproject('proc-macro2').get_variable('proc_macro2_de= p') + +_quote_rs =3D static_library( + 'quote', + files('src/lib.rs'), + gnu_symbol_visibility: 'hidden', + rust_abi: 'rust', + rust_args: [ + '--edition', '2021', + '--cfg', 'feature=3D"proc-macro"', + ], + dependencies: [ + proc_macro2_dep, + ], +) + +quote_dep =3D declare_dependency( + link_with: _quote_rs, +) + diff --git a/subprojects/packagefiles/syn/meson.build b/subprojects/package= files/syn/meson.build new file mode 100644 index 0000000000..104791f5c7 --- /dev/null +++ b/subprojects/packagefiles/syn/meson.build @@ -0,0 +1,33 @@ +project('syn', 'rust', + version: '2.0.66', + license: 'GPL-2.0-or-later', + default_options: []) + +quote_dep =3D subproject('quote').get_variable('quote_dep') +proc_macro2_dep =3D subproject('proc-macro2').get_variable('proc_macro2_de= p') +unicode_ident_dep =3D subproject('unicode-ident').get_variable('unicode_id= ent_dep') + +_syn_rs =3D static_library( + 'syn', + files('src/lib.rs'), + gnu_symbol_visibility: 'hidden', + rust_abi: 'rust', + rust_args: [ + '--edition', '2021', + '--cfg', 'feature=3D"full"', + '--cfg', 'feature=3D"derive"', + '--cfg', 'feature=3D"parsing"', + '--cfg', 'feature=3D"printing"', + '--cfg', 'feature=3D"clone-impls"', + '--cfg', 'feature=3D"proc-macro"', + ], + dependencies: [ + quote_dep, + proc_macro2_dep, + unicode_ident_dep, + ], +) + +syn_dep =3D declare_dependency( + link_with: _syn_rs, +) diff --git a/subprojects/packagefiles/unicode-ident/meson.build b/subprojec= ts/packagefiles/unicode-ident/meson.build new file mode 100644 index 0000000000..c81217de09 --- /dev/null +++ b/subprojects/packagefiles/unicode-ident/meson.build @@ -0,0 +1,19 @@ +project('unicode-ident', 'rust', + version: '1.0.12', + license: 'GPL-2.0-or-later', + default_options: []) + +_unicode_ident_rs =3D static_library( + 'unicode_ident', + files('src/lib.rs'), + gnu_symbol_visibility: 'hidden', + rust_abi: 'rust', + rust_args: [ + '--edition', '2021', + ], + dependencies: [], +) + +unicode_ident_dep =3D declare_dependency( + link_with: _unicode_ident_rs, +) diff --git a/subprojects/proc-macro-error-attr.wrap b/subprojects/proc-macr= o-error-attr.wrap new file mode 100644 index 0000000000..f24dbaadf3 --- /dev/null +++ b/subprojects/proc-macro-error-attr.wrap @@ -0,0 +1,10 @@ +[wrap-file] +directory =3D proc-macro-error-attr-1.0.4 +source_url =3D https://crates.io/api/v1/crates/proc-macro-error-attr/1.0.4= /download +source_filename =3D proc-macro-erro-attrr-1.0.4.tar.gz +source_hash =3D a1be40180e52ecc98ad80b184934baf3d0d29f979574e439af5a55274b= 35f869 +#method =3D cargo +patch_directory =3D proc-macro-error-attr + +[provide] +dependency_names =3D proc_macro_error_attr_dep diff --git a/subprojects/proc-macro-error.wrap b/subprojects/proc-macro-err= or.wrap new file mode 100644 index 0000000000..95110ef94f --- /dev/null +++ b/subprojects/proc-macro-error.wrap @@ -0,0 +1,11 @@ +[wrap-file] +directory =3D proc-macro-error-1.0.4 +source_url =3D https://crates.io/api/v1/crates/proc-macro-error/1.0.4/down= load +source_filename =3D proc-macro-error-1.0.4.tar.gz +source_hash =3D da25490ff9892aab3fcf7c36f08cfb902dd3e71ca0f9f9517bea02a73a= 5ce38c +#method =3D cargo +patch_directory =3D proc-macro-error + +[provide] +dependency_names =3D proc_macro_error_dep + diff --git a/subprojects/proc-macro2.wrap b/subprojects/proc-macro2.wrap new file mode 100644 index 0000000000..70849b9944 --- /dev/null +++ b/subprojects/proc-macro2.wrap @@ -0,0 +1,10 @@ +[wrap-file] +directory =3D proc-macro2-1.0.84 +source_url =3D https://crates.io/api/v1/crates/proc-macro2/1.0.84/download +source_filename =3D proc-macro2-1.0.84.0.tar.gz +source_hash =3D ec96c6a92621310b51366f1e28d05ef11489516e93be030060e5fc1202= 4a49d6 +#method =3D cargo +patch_directory =3D proc-macro2 + +[provide] +dependency_names =3D proc_macro2_dep diff --git a/subprojects/quote.wrap b/subprojects/quote.wrap new file mode 100644 index 0000000000..82836107cb --- /dev/null +++ b/subprojects/quote.wrap @@ -0,0 +1,10 @@ +[wrap-file] +directory =3D quote-1.0.36 +source_url =3D https://crates.io/api/v1/crates/quote/1.0.36/download +source_filename =3D quote-1.0.36.0.tar.gz +source_hash =3D 0fa76aaf39101c457836aec0ce2316dbdc3ab723cdda1c6bd4e6ad4208= acaca7 +#method =3D cargo +patch_directory =3D quote + +[provide] +dependency_names =3D quote_dep diff --git a/subprojects/syn.wrap b/subprojects/syn.wrap new file mode 100644 index 0000000000..f5ebe033de --- /dev/null +++ b/subprojects/syn.wrap @@ -0,0 +1,11 @@ +[wrap-file] +directory =3D syn-2.0.66 +source_url =3D https://crates.io/api/v1/crates/syn/2.0.66/download +source_filename =3D syn-2.0.66.0.tar.gz +source_hash =3D c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3= cdcff5 +#method =3D cargo +patch_directory =3D syn + +[provide] +dependency_names =3D syn_dep + diff --git a/subprojects/unicode-ident.wrap b/subprojects/unicode-ident.wrap new file mode 100644 index 0000000000..7b5304ccac --- /dev/null +++ b/subprojects/unicode-ident.wrap @@ -0,0 +1,10 @@ +[wrap-file] +directory =3D unicode-ident-1.0.12 +source_url =3D https://crates.io/api/v1/crates/unicode-ident/1.0.12/downlo= ad +source_filename =3D unicode-ident-1.0.12.tar.gz +source_hash =3D 3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec= 0fee4b +#method =3D cargo +patch_directory =3D unicode-ident + +[provide] +dependency_names =3D unicode_ident_dep --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89