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[37.6.160.241]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a2ca5casm22471015e9.32.2024.07.04.05.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 05:15:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720095356; x=1720700156; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hS0Lhnq0ub+oR2j0gfm0V0iTzo6BJYZeeH7eXts0Kaw=; b=crLPjKpT+MRDjpqVRMzq0UXdIwBU6Hlz6Njeo3BBO/BIEqux3JTBYy+nEJ9oa7hS7K 4tTGCnxnQB3cji2DoCUFxSpZzFVVyJvKQoYEJamgqQJ5Zviy3cU3DCTUzK35THDTE1sP KlSPcIJDCZmI202JoXXTohS7YIAW6Xu1kW7ThwsPWlrup5h842snB5sOXoReVj7HlWni KptIa1fzsBCuMINAggJifxzzpoZBqLsDom7aYzEKtcQNJnjteo6WWrx4shJg2475sKr+ N1zW+PEozV2FkvNSjVEV4TrxHOoiOGgQUtfMmD2FIiqrz44WS9TBd+wflYMFkmpkH5U/ Ja9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720095356; x=1720700156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hS0Lhnq0ub+oR2j0gfm0V0iTzo6BJYZeeH7eXts0Kaw=; b=VFMkzQIOPZ8DDCiQuYhys/PmWGMfh68yFqf1RiCyzqUt+P39KTelJXp/doil8vjVZi xy5iZZithvTYFNmrr7irPEzAssOCRulhhn3irmMhQE9VrrLJ9WqsAfld4MiVlj2RKi9M msyz5IkI/TIko+2qLyg8lzphWOo+VBbTgWkA0epQml++pSncHks2LENjI/8oSpApPTLj cv3Fje5voBDuVcdyyK9f99NZgDBckiq25lfSSy7ngmOhimkCJJUeQHKO/mwlCMTbIQb+ 74CNy8tlH0ayHUpzvURERf3BZFfbLLeiTrwoFB68quephlM0V4onjcvQ42lv16Re/WNz wfyQ== X-Gm-Message-State: AOJu0YytukstvLH+SfvQ35CgOk/Z3EzQ8wqxOttaG0ome7AYoiS+xUvG yN42x1v9Nli9i+q1vyp7+QqcBNKaB3vwZnYvvFJEyp2rVcX99aLaCOfZKKFxUGWGRsz+5DmM7Tf bYnw= X-Google-Smtp-Source: AGHT+IHzRHMDXaZdadaT9o6rjkbm9o22rGbLSPF3ap3w5u/y4Mn+lFWPO8cTMPPLVahqIA17DTR/mg== X-Received: by 2002:a05:651c:105c:b0:2ec:57c7:c737 with SMTP id 38308e7fff4ca-2ee8edfead1mr10418981fa.40.1720095354847; Thu, 04 Jul 2024 05:15:54 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson , Paolo Bonzini , John Snow , Cleber Rosa Subject: [RFC PATCH v4 1/7] build-sys: Add rust feature option Date: Thu, 4 Jul 2024 15:15:37 +0300 Message-ID: <12f78335f01f2264b91b3170995aa86ccae7d0cb.1720094395.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720095442672100012 Add options for Rust in meson_options.txt, meson.build, configure to prepare for adding Rust code in the followup commits. `rust` is a reserved meson name, so we have to use an alternative. `with_rust` was chosen. A cargo_wrapper.py script is added that is heavily based on the work of Marc-Andr=C3=A9 Lureau from 2021. https://patchew.org/QEMU/20210907121943.3498701-1-marcandre.lureau@redhat.c= om/ Signed-off-by: Marc-Andr=C3=A9 Lureau Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 5 + configure | 11 ++ meson.build | 11 ++ meson_options.txt | 5 + scripts/cargo_wrapper.py | 294 ++++++++++++++++++++++++++++++++++ scripts/meson-buildoptions.sh | 6 + 6 files changed, 332 insertions(+) create mode 100644 scripts/cargo_wrapper.py diff --git a/MAINTAINERS b/MAINTAINERS index 6725913c8b..d01bd06ab7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4226,6 +4226,11 @@ F: docs/sphinx/ F: docs/_templates/ F: docs/devel/docs.rst =20 +Rust build system integration +M: Manos Pitsidianakis +S: Maintained +F: scripts/cargo_wrapper.py + Miscellaneous ------------- Performance Tools and Tests diff --git a/configure b/configure index 8b6a2f16ce..180d87b9c9 100755 --- a/configure +++ b/configure @@ -302,6 +302,9 @@ else objcc=3D"${objcc-${cross_prefix}clang}" fi =20 +with_rust=3D"auto" +with_rust_target_triple=3D"" + ar=3D"${AR-${cross_prefix}ar}" as=3D"${AS-${cross_prefix}as}" ccas=3D"${CCAS-$cc}" @@ -757,6 +760,12 @@ for opt do ;; --gdb=3D*) gdb_bin=3D"$optarg" ;; + --enable-with-rust) with_rust=3Denabled + ;; + --disable-with-rust) with_rust=3Ddisabled + ;; + --with-rust-target-triple=3D*) with_rust_target_triple=3D"$optarg" + ;; # everything else has the same name in configure and meson --*) meson_option_parse "$opt" "$optarg" ;; @@ -1789,6 +1798,8 @@ if test "$skip_meson" =3D no; then test -n "${LIB_FUZZING_ENGINE+xxx}" && meson_option_add "-Dfuzzing_engin= e=3D$LIB_FUZZING_ENGINE" test "$plugins" =3D yes && meson_option_add "-Dplugins=3Dtrue" test "$tcg" !=3D enabled && meson_option_add "-Dtcg=3D$tcg" + test "$with_rust" !=3D enabled && meson_option_add "-Dwith_rust=3D$with_= rust" + test "$with_rust_target_triple" !=3D "" && meson_option_add "-Dwith_rust= _target_triple=3D$with_rust_target_triple" run_meson() { NINJA=3D$ninja $meson setup "$@" "$PWD" "$source_path" } diff --git a/meson.build b/meson.build index 2f981f936e..11b8b146da 100644 --- a/meson.build +++ b/meson.build @@ -290,6 +290,12 @@ foreach lang : all_languages endif endforeach =20 +cargo =3D not_found +if get_option('with_rust').allowed() + cargo =3D find_program('cargo', required: get_option('with_rust')) +endif +with_rust =3D cargo.found() + # default flags for all hosts # We use -fwrapv to tell the compiler that we require a C dialect where # left shift of signed integers is well defined and has the expected @@ -2118,6 +2124,7 @@ endif =20 config_host_data =3D configuration_data() =20 +config_host_data.set('CONFIG_WITH_RUST', with_rust) audio_drivers_selected =3D [] if have_system audio_drivers_available =3D { @@ -4243,6 +4250,10 @@ if 'objc' in all_languages else summary_info +=3D {'Objective-C compiler': false} endif +summary_info +=3D {'Rust support': with_rust} +if with_rust and get_option('with_rust_target_triple') !=3D '' + summary_info +=3D {'Rust target': get_option('with_rust_target_tripl= e')} +endif option_cflags =3D (get_option('debug') ? ['-g'] : []) if get_option('optimization') !=3D 'plain' option_cflags +=3D ['-O' + get_option('optimization')] diff --git a/meson_options.txt b/meson_options.txt index 0269fa0f16..3443c48001 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -371,3 +371,8 @@ option('hexagon_idef_parser', type : 'boolean', value := true, =20 option('x86_version', type : 'combo', choices : ['0', '1', '2', '3', '4'],= value: '1', description: 'tweak required x86_64 architecture version beyond com= piler default') + +option('with_rust', type: 'feature', value: 'auto', + description: 'Enable Rust support') +option('with_rust_target_triple', type : 'string', value: '', + description: 'Override Rust target triple') diff --git a/scripts/cargo_wrapper.py b/scripts/cargo_wrapper.py new file mode 100644 index 0000000000..d2c7265461 --- /dev/null +++ b/scripts/cargo_wrapper.py @@ -0,0 +1,294 @@ +#!/usr/bin/env python3 + +"""Wrap cargo builds for meson integration + +This program builds Rust library crates and makes sure: + - They receive the correct --cfg compile flags from the QEMU build that c= alls + it. + - They receive the generated Rust bindings path so that they can copy it + inside their output subdirectories. + - Cargo puts all its build artifacts in the appropriate meson build direc= tory. + - The produced static libraries are copied to the path the caller (meson) + defines. + +Copyright (c) 2020 Red Hat, Inc. +Copyright (c) 2024 Linaro Ltd. + +Authors: + Marc-Andr=C3=A9 Lureau + Manos Pitsidianakis + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . +""" + + +import argparse +import json +import logging +import os +import subprocess +import sys +import shutil + +from pathlib import Path +from typing import Any, Dict, List + + +def generate_cfg_flags(header: str) -> List[str]: + """Converts defines from config[..].h headers to rustc --cfg flags.""" + + def cfg_name(name: str) -> str: + """Filter function for C #defines""" + if ( + name.startswith("CONFIG_") + or name.startswith("TARGET_") + or name.startswith("HAVE_") + ): + return name + return "" + + with open(header, encoding=3D"utf-8") as cfg: + config =3D [l.split()[1:] for l in cfg if l.startswith("#define")] + + cfg_list =3D [] + for cfg in config: + name =3D cfg_name(cfg[0]) + if not name: + continue + if len(cfg) >=3D 2 and cfg[1] !=3D "1": + continue + cfg_list.append("--cfg") + cfg_list.append(name) + return cfg_list + + +def cargo_target_dir(args: argparse.Namespace) -> Path: + """Place cargo's build artifacts into meson's build directory""" + return args.private_dir + + +def manifest_path(args: argparse.Namespace) -> Path: + """Returns the Cargo.toml manifest path""" + return args.crate_dir / "Cargo.toml" + + +def get_cargo_rustc(args: argparse.Namespace) -> tuple[Dict[str, Any], Lis= t[str]]: + """Returns the appropriate cargo invocation and environment""" + + # See https://doc.rust-lang.org/cargo/reference/environment-variables.= html + # Item `CARGO_ENCODED_RUSTFLAGS =E2=80=94 A list of custom flags separ= ated by + # 0x1f (ASCII Unit Separator) to pass to all compiler invocations that= Cargo + # performs` + cfg =3D chr(0x1F).join( + [c for h in args.config_headers for c in generate_cfg_flags(h)] + ) + target_dir =3D cargo_target_dir(args) + cargo_path =3D manifest_path(args) + + cargo_cmd =3D [ + "cargo", + "build", + "--target-dir", + str(target_dir), + "--manifest-path", + str(cargo_path), + ] + if args.target_triple: + cargo_cmd +=3D ["--target", args.target_triple] + if args.profile =3D=3D "release": + cargo_cmd +=3D ["--release"] + + env =3D os.environ + env["CARGO_ENCODED_RUSTFLAGS"] =3D cfg + + return (env, cargo_cmd) + + +def run_cargo(env: Dict[str, Any], cargo_cmd: List[str]) -> str: + """Calls cargo build invocation.""" + envlog =3D " ".join([f"{k}=3D{v}" for k, v in env.items()]) + cmdlog =3D " ".join(cargo_cmd) + logging.debug("Running %s %s", envlog, cmdlog) + try: + out =3D subprocess.check_output( + cargo_cmd, + env=3Ddict(os.environ, **env), + stderr=3Dsubprocess.STDOUT, + universal_newlines=3DTrue, + ) + except subprocess.CalledProcessError as err: + print("Environment: " + envlog) + print("Command: " + cmdlog) + print(err.output) + sys.exit(1) + + return out + + +def get_package_name(cargo_toml_path: Path) -> str: + """Attempts to get package name from cargo manifest file with toml par= sing libraries.""" + # pylint: disable=3Dimport-outside-toplevel + + try: + import tomllib + except ImportError: + import tomli as tomllib + with open(cargo_toml_path, "rb") as toml_file: + config =3D tomllib.load(toml_file) + + package_name =3D config["package"]["name"].strip('"').replace("-", "_") + return package_name + + +def get_package_name_json(cargo_toml_path: Path) -> str: + """Attempts to get package name from cargo-metadata output which has a= standard JSON format.""" + + cmd =3D [ + "cargo", + "metadata", + "--format-version", + "1", + "--no-deps", + "--manifest-path", + str(cargo_toml_path), + "--offline", + ] + try: + out =3D subprocess.check_output( + cmd, + env=3Dos.environ, + stderr=3Dsubprocess.STDOUT, + universal_newlines=3DTrue, + ) + except subprocess.CalledProcessError as err: + print("Command: ", " ".join(cmd)) + print(err.output) + raise err + package_name =3D json.loads(out)["packages"][0]["name"].strip('"').rep= lace("-", "_") + return package_name + + +def build_lib(args: argparse.Namespace) -> None: + """Builds Rust lib given by command line arguments.""" + + logging.debug("build-lib") + target_dir =3D cargo_target_dir(args) + cargo_toml_path =3D manifest_path(args) + + try: + # If we have tomllib or tomli, parse the .toml file + package_name =3D get_package_name(cargo_toml_path) + except ImportError as import_exc: + try: + # Parse the json output of cargo-metadata as a fallback + package_name =3D get_package_name_json(cargo_toml_path) + except Exception as exc: + raise exc from import_exc + + liba_filename =3D "lib" + package_name + ".a" + profile_dir =3D args.profile + if args.profile =3D=3D "dev": + profile_dir =3D "debug" + + liba =3D target_dir / args.target_triple / profile_dir / liba_filename + + env, cargo_cmd =3D get_cargo_rustc(args) + out =3D run_cargo(env, cargo_cmd) + logging.debug("cargo output: %s", out) + logging.debug("cp %s %s", liba, args.outdir) + shutil.copy2(liba, args.outdir) + + +def main() -> None: + # pylint: disable=3Dmissing-function-docstring + parser =3D argparse.ArgumentParser() + parser.add_argument("-v", "--verbose", action=3D"store_true") + parser.add_argument( + "--color", + metavar=3D"WHEN", + choices=3D["auto", "always", "never"], + default=3D"auto", + help=3D"Coloring: auto, always, never", + ) + parser.add_argument( + "--config-headers", + metavar=3D"CONFIG_HEADER", + action=3D"append", + dest=3D"config_headers", + help=3D"paths to any configuration C headers (*.h files), if any", + required=3DFalse, + default=3D[], + ) + parser.add_argument( + "--meson-build-dir", + metavar=3D"BUILD_DIR", + help=3D"meson.current_build_dir()", + type=3DPath, + dest=3D"meson_build_dir", + required=3DTrue, + ) + parser.add_argument( + "--meson-source-dir", + metavar=3D"SOURCE_DIR", + help=3D"meson.current_source_dir()", + type=3DPath, + dest=3D"meson_build_dir", + required=3DTrue, + ) + parser.add_argument( + "--crate-dir", + metavar=3D"CRATE_DIR", + type=3DPath, + dest=3D"crate_dir", + help=3D"Absolute path that contains the manifest file of the crate= to compile. Example: '/path/to/qemu/rust/pl011'", + required=3DTrue, + ) + parser.add_argument( + "--outdir", + metavar=3D"OUTDIR", + type=3DPath, + dest=3D"outdir", + help=3D"Destination path to copy compiled artifacts to for Meson t= o use. Example values: '/path/to/qemu/build', '.'", + required=3DTrue, + ) + # using @PRIVATE_DIR@ is necessary for `ninja clean` to clean up rust'= s intermediate build artifacts. + # NOTE: at the moment cleanup doesn't work due to a bug: https://githu= b.com/mesonbuild/meson/issues/7584 + parser.add_argument( + "--private-dir", + metavar=3D"PRIVATE_DIR", + type=3DPath, + dest=3D"private_dir", + help=3D"Override cargo's target directory with a meson provided pr= ivate directory.", + required=3DTrue, + ) + parser.add_argument( + "--profile", type=3Dstr, choices=3D["release", "dev"], required=3D= True + ) + parser.add_argument("--target-triple", type=3Dstr, required=3DTrue) + + subparsers =3D parser.add_subparsers() + + buildlib =3D subparsers.add_parser("build-lib") + buildlib.set_defaults(func=3Dbuild_lib) + + args =3D parser.parse_args() + if args.verbose: + logging.basicConfig(level=3Dlogging.DEBUG) + logging.debug("args: %s", args) + + args.func(args) + + +if __name__ =3D=3D "__main__": + main() diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index cfadb5ea86..23a24ccaa7 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -79,6 +79,8 @@ meson_options_help() { printf "%s\n" ' auto/sigaltstack/ucontext/wind= ows)' printf "%s\n" ' --with-pkgversion=3DVALUE use specified string as sub-= version of the' printf "%s\n" ' package' + printf "%s\n" ' --with-rust-target-triple=3DVALUE' + printf "%s\n" ' Specify Rust host target tripl= e' printf "%s\n" ' --with-suffix=3DVALUE Suffix for QEMU data/modules= /config directories' printf "%s\n" ' (can be empty) [qemu]' printf "%s\n" ' --with-trace-file=3DVALUE Trace file prefix for simple= backend [trace]' @@ -216,6 +218,7 @@ meson_options_help() { printf "%s\n" ' vvfat vvfat image format support' printf "%s\n" ' werror Treat warnings as errors' printf "%s\n" ' whpx WHPX acceleration support' + printf "%s\n" ' with-rust Enable Rust support' printf "%s\n" ' xen Xen backend support' printf "%s\n" ' xen-pci-passthrough' printf "%s\n" ' Xen PCI passthrough support' @@ -552,6 +555,9 @@ _meson_option_parse() { --enable-whpx) printf "%s" -Dwhpx=3Denabled ;; --disable-whpx) printf "%s" -Dwhpx=3Ddisabled ;; --x86-version=3D*) quote_sh "-Dx86_version=3D$2" ;; + --enable-with-rust) printf "%s" -Dwith_rust=3Denabled ;; + --disable-with-rust) printf "%s" -Dwith_rust=3Ddisabled ;; + --with-rust-target-triple=3D*) quote_sh "-Dwith_rust_target_triple=3D$= 2" ;; --enable-xen) printf "%s" -Dxen=3Denabled ;; --disable-xen) printf "%s" -Dxen=3Ddisabled ;; --enable-xen-pci-passthrough) printf "%s" -Dxen_pci_passthrough=3Denab= led ;; --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89 From nobody Sun Nov 24 20:49:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1720095443; cv=none; d=zohomail.com; s=zohoarc; b=P0U5QF0Up9jhN5n3Iik6DEy3ZUwL0sl0KJNlPI9299aYA0uJdye4qWkVz7iNty5wCjj2gnWZLyKS7eGSBsdY4wPiTGuphGgfnUfoXNwCWj4rMVFhl0kdkJgzbMdGS/9yPiaIDgapxiB5NpuKI+22cRtVrnZH8Hsm8XomalId/9g= ARC-Message-Signature: i=1; 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[37.6.160.241]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a2ca5casm22471015e9.32.2024.07.04.05.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 05:15:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720095359; x=1720700159; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9wdmH73h+dBKRqM1kMpHUr/tBq0w0+7ozYuWaUzEdN8=; b=kMyEck179WRiFWmQbp2zxPwN0qUnopiwpeMkS/muPv1NMDf/82Drio/BrLSQyDLHZ5 2wyVG2lseXrniSSzl+FZsxYbc36re5azkEB/crtw/IQEsDJqKxpeLS7RcBo8dU+OifLz uEw5aG9MX2TeNwvYQCsu+TEZgESavNR5XpKRJNMvZod+ViObSAh9dGbZLGdOMh9R/w9f /LWH9cclzC0uVRYB6PKTSIWyVwWL06NqAo4NuGJsS3efLHnVQFebeknCFkdQS+74oqKg 006I2zo3SAp95ZSVc+4+v5Q/cIOcWyIyNiw33mqUKDc7WTjFd6+sdxlZLR+9e9qyA/DC umvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720095359; x=1720700159; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9wdmH73h+dBKRqM1kMpHUr/tBq0w0+7ozYuWaUzEdN8=; b=FXKgdzUs62qEFixhrq8f8EvXnh79ozzdAd3FeMRpIK2o/QllTeZmaM2G9zMxBGB74D cL8wZNYKClL/fVws3/uAM5AarqQKPMT2iGG321Vo2MGIPb+mviG2S6LaBmwpgIZgV2h3 Mb41ml3BJvAaZ4vHbFL6ISfV7KZGm+DB/HFHZjcS9X/57u6fcGQdyIDZ2MCCT9wh5ZjA TSXDlC+jf4YllJEQlSaoLiBZUbXolXYwLv2ncIFJ+N8iQrk6wNYD7Ex45NDggNBxZI5v UjN+iDZbIDVZR6+jL+70Y6OUxpEyMu0C9v4QLtXJA578RsltDMSJfjpXf7QOHhYyeMK0 5bxg== X-Gm-Message-State: AOJu0YyO/1Cde6JfzfEA9vSxHU7aCXV0f3DDmtH8eEKKWZHCcZ6XOPA+ J/Gz8t3wQhJJog6rP24D+hr0Hoyd17La/dgXYPsVXVXS+wy0u1S/KHW64BW6PhwvOlAG/hbbbMk VmWM= X-Google-Smtp-Source: AGHT+IErY6rE5qtxu0L1+UIaWbA/c6C9IB8wm+aMHi/LbXJETKPxeKHUM2EX1nQhpNBOFbK83y+YQQ== X-Received: by 2002:a05:600c:364d:b0:425:5f6d:b4a with SMTP id 5b1f17b1804b1-4264a3e3182mr11164255e9.9.1720095358937; Thu, 04 Jul 2024 05:15:58 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson , Paolo Bonzini , John Snow , Cleber Rosa Subject: [RFC PATCH v4 2/7] rust: add bindgen step as a meson dependency Date: Thu, 4 Jul 2024 15:15:38 +0300 Message-ID: <4ce5a7330f594c6c94c8cc3aabceb061095bb855.1720094395.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720095444411100015 Content-Type: text/plain; charset="utf-8" Add mechanism to generate rust hw targets that depend on a custom bindgen target for rust bindings to C. This way bindings will be created before the rust crate is compiled. The bindings will end up in BUILDDIR/{target}-generated.rs and have the sam= e name as a target: ninja aarch64-softmmu-generated.rs The way the bindings are generated is: 1. All required C headers are included in a single file, in our case rust/wrapper.h for convenience. Otherwise we'd have to provide a list of headers every time to the bindgen tool. 2. Meson creates a generated_rs target that runs bindgen making sure the architecture etc header dependencies are present. 3. The generated_rs target takes a list of files, type symbols, function symbols to block from being generated. This is not necessary for the bindings to work, but saves us time and space. 4. Meson creates rust hardware target dependencies from the rust_targets dictionary defined in rust/meson.build. Since we cannot declare a dependency on generated_rs before it is declared in meson.build, the rust crate targets must be defined after the generated_rs target for each target architecture is defined. This way meson sets up the dependency tree properly. 5. After compiling each rust crate with the cargo_wrapper.py script, its static library artifact is linked as a `whole-archive` with the final binary. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 3 ++ meson.build | 57 ++++++++++++++++++++ rust/.gitignore | 3 ++ rust/meson.build | 112 +++++++++++++++++++++++++++++++++++++++ rust/wrapper.h | 39 ++++++++++++++ scripts/cargo_wrapper.py | 18 +++---- 6 files changed, 220 insertions(+), 12 deletions(-) create mode 100644 rust/.gitignore create mode 100644 rust/meson.build create mode 100644 rust/wrapper.h diff --git a/MAINTAINERS b/MAINTAINERS index d01bd06ab7..6e7b8207fb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4230,6 +4230,9 @@ Rust build system integration M: Manos Pitsidianakis S: Maintained F: scripts/cargo_wrapper.py +F: rust/meson.build +F: rust/wrapper.h +F: rust/.gitignore =20 Miscellaneous ------------- diff --git a/meson.build b/meson.build index 11b8b146da..71011fd3b3 100644 --- a/meson.build +++ b/meson.build @@ -3929,6 +3929,63 @@ foreach target : target_dirs lib_deps +=3D dep.partial_dependency(compile_args: true, includes: tru= e) endforeach =20 + if with_rust and target_type =3D=3D 'system' + # FIXME: meson outputs the following warnings, which should be reso= lved + # before merging: + # > WARNING: Project specifies a minimum meson_version '>=3D0.63.0'= but + # > uses features which were added in newer versions: + # > * 0.64.0: {'fs.copyfile'} + # > * 1.0.0: {'dependencies arg in rust.bindgen', 'module rust as s= table module'} + rust_bindgen =3D import('rust') + + # We need one bindings_rs build target per arch target, so give them + # arch-specific names. + copy =3D fs.copyfile('rust/wrapper.h', + target + '_wrapper.h') + bindings_rs =3D rust_bindgen.bindgen( + input: copy, + dependencies: arch_deps + lib_deps, + output: 'bindings-' + target + '.rs', + include_directories: include_directories('.', 'include'), + args: [ + '--ctypes-prefix', 'core::ffi', + '--formatter', 'rustfmt', + '--generate-block', + '--generate-cstr', + '--impl-debug', + '--merge-extern-blocks', + '--no-doc-comments', + '--no-include-path-detection', + '--use-core', + '--with-derive-default', + '--allowlist-file', meson.project_source_root() + '/include/.*', + '--allowlist-file', meson.project_source_root() + '/.*', + '--allowlist-file', meson.project_build_root() + '/.*' + ], + ) + + if target in rust_targets + rust_hw =3D ss.source_set() + foreach t: rust_targets[target] + rust_device_cargo_build =3D custom_target(t['name'], + output: t['output'], + depends: [bindings_rs], + build_always_stale: true, + command: t['command']) + rust_dep =3D declare_dependency(link_args: [ + '-Wl,--whole-archive', + t['output'], + '-Wl,--no-whole-archive' + ], + sources: [rust_device_cargo_buil= d]) + rust_hw.add(rust_dep) + endforeach + rust_hw_config =3D rust_hw.apply(config_target, strict: false) + arch_srcs +=3D rust_hw_config.sources() + arch_deps +=3D rust_hw_config.dependencies() + endif + endif + lib =3D static_library('qemu-' + target, sources: arch_srcs + genh, dependencies: lib_deps, diff --git a/rust/.gitignore b/rust/.gitignore new file mode 100644 index 0000000000..1bf71b1f68 --- /dev/null +++ b/rust/.gitignore @@ -0,0 +1,3 @@ +# Ignore any cargo development build artifacts; for qemu-wide builds, all = build +# artifacts will go to the meson build directory. +target diff --git a/rust/meson.build b/rust/meson.build new file mode 100644 index 0000000000..5fdc2621a3 --- /dev/null +++ b/rust/meson.build @@ -0,0 +1,112 @@ +# Supported hosts +rust_supported_oses =3D { + 'linux': '-unknown-linux-gnu', + # 'darwin': '-apple-darwin', + # 'windows': '-pc-windows-gnu' +} +rust_supported_cpus =3D ['x86_64', 'aarch64'] + +# Future-proof the above definitions against any change in the root meson.= build file: +foreach rust_os: rust_supported_oses.keys() + if not supported_oses.contains(rust_os) + message() + warning('UNSUPPORTED OS VALUES IN ' + meson.current_source_dir() + '/m= eson.build') + message() + message('This meson.build file claims OS `+' + rust_os + '` is support= ed but') + message('it is not included in the global supported OSes list in') + message(meson.global_source_root() + '/meson.build.') + endif +endforeach +foreach rust_cpu: rust_supported_cpus + if not supported_cpus.contains(rust_cpu) + message() + warning('UNSUPPORTED CPU VALUES IN ' + meson.current_source_dir() + '/= meson.build') + message() + message('This meson.build file claims CPU `+' + rust_cpu + '` is suppo= rted but') + message('it is not included in the global supported CPUs list in') + message(meson.global_source_root() + '/meson.build.') + endif +endforeach + +msrv =3D { + 'rustc': '1.77.2', + 'cargo': '1.77.2', + 'bindgen': '0.69.4', +} + +foreach bin_dep: msrv.keys() + bin =3D find_program(bin_dep, required: true) + if bin.version() < msrv[bin_dep] + message() + error(bin_dep + ' version ' + bin.version() + ' is unsupported: Please= upgrade to at least ' + msrv[bin_dep]) + endif +endforeach + +rust_target_triple =3D get_option('with_rust_target_triple') + +if rust_target_triple =3D=3D '' + if not supported_oses.contains(host_os) + message() + error('QEMU does not support `' + host_os +'` as a Rust platform.') + elif not supported_cpus.contains(host_arch) + message() + error('QEMU does not support `' + host_arch +'` as a Rust architecture= .') + endif + rust_target_triple =3D host_arch + rust_supported_oses[host_os] + # if host_os =3D=3D 'windows' and host_arch =3D=3D 'aarch64' + # rust_target_triple +=3D 'llvm' + # endif +else + # verify rust_target_triple if given as an option + rustc =3D find_program('rustc', required: true) + rustc_targets =3D run_command(rustc, '--print', 'target-list', capture: = true, check: true).stdout().strip().split() + if not rustc_targets.contains(rust_target_triple) + message() + error('Given rust_target_triple ' + rust_target_triple + ' is not list= ed in rustc --print target-list output') + endif +endif + +rust_targets =3D {} + +cargo_wrapper =3D [ + find_program(meson.global_source_root() / 'scripts/cargo_wrapper.py'), + '--config-headers', meson.project_build_root() / 'config-host.h', + '--meson-build-root', meson.project_build_root(), +] + +if get_option('b_colorout') !=3D 'never' + cargo_wrapper +=3D ['--color', 'always'] +endif + +if get_option('optimization') in ['0', '1', 'g'] + rs_build_profile =3D 'dev' +else + rs_build_profile =3D 'release' +endif + +subdir('qemu-api') + +# Collect metadata for each (crate,qemu-target,compiler-target) combinatio= n. +# Rust meson targets cannot be defined a priori because they depend on bin= dgen +# generation that is created for each emulation target separately. Thus Ru= st +# meson targets will be defined for each target after the target-specific +# bindgen dependency is declared. +rust_hw_target_list =3D {} + +foreach rust_hw_target, rust_hws: rust_hw_target_list + foreach rust_hw_dev: rust_hws + crate_metadata =3D { + 'name': rust_hw_dev['name'], + 'output': [rust_hw_dev['output']], + 'command': [cargo_wrapper, + '--crate-dir', meson.current_source_dir() / rust_hw_dev['dirname'], + '--profile', rs_build_profile, + '--target-triple', rust_target_triple, + '--private-dir', '@PRIVATE_DIR@', + '--outdir', '@OUTDIR@', + 'build-lib' + ] + } + rust_targets +=3D { rust_hw_target: [crate_metadata] } + endforeach +endforeach diff --git a/rust/wrapper.h b/rust/wrapper.h new file mode 100644 index 0000000000..51985f0ef1 --- /dev/null +++ b/rust/wrapper.h @@ -0,0 +1,39 @@ +/* + * QEMU System Emulator + * + * Copyright 2024 Manos Pitsidianakis + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "qemu-io.h" +#include "sysemu/sysemu.h" +#include "hw/sysbus.h" +#include "exec/memory.h" +#include "chardev/char-fe.h" +#include "hw/clock.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "hw/irq.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "chardev/char-serial.h" diff --git a/scripts/cargo_wrapper.py b/scripts/cargo_wrapper.py index d2c7265461..e7d9238c16 100644 --- a/scripts/cargo_wrapper.py +++ b/scripts/cargo_wrapper.py @@ -111,6 +111,8 @@ def get_cargo_rustc(args: argparse.Namespace) -> tuple[= Dict[str, Any], List[str] =20 env =3D os.environ env["CARGO_ENCODED_RUSTFLAGS"] =3D cfg + env["MESON_BUILD_DIR"] =3D str(target_dir) + env["MESON_BUILD_ROOT"] =3D str(args.meson_build_root) =20 return (env, cargo_cmd) =20 @@ -231,19 +233,11 @@ def main() -> None: default=3D[], ) parser.add_argument( - "--meson-build-dir", - metavar=3D"BUILD_DIR", - help=3D"meson.current_build_dir()", + "--meson-build-root", + metavar=3D"BUILD_ROOT", + help=3D"meson.project_build_root(): the root build directory. Exam= ple: '/path/to/qemu/build'", type=3DPath, - dest=3D"meson_build_dir", - required=3DTrue, - ) - parser.add_argument( - "--meson-source-dir", - metavar=3D"SOURCE_DIR", - help=3D"meson.current_source_dir()", - type=3DPath, - dest=3D"meson_build_dir", + dest=3D"meson_build_root", required=3DTrue, ) parser.add_argument( --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89 From nobody Sun Nov 24 20:49:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1720095470; cv=none; d=zohomail.com; s=zohoarc; b=XRBLVsngtoo7ObRxyIqsM5t0G5xKOmR0rlTqRDnUSi/S+jxuIK/04PWqxH9BHJf/bZw+rSKUVRRE8jtx0XgxyVTTmgLdAMzhaN81wZZyPkQ/VR5EeiFFjZk4Hz/j2F+1UpA0Ypn13Rm8JhzbszTUSVFztQqXNk4QGDgfzjvzsM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720095470; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eoRb5gNelpL+/SZJuMxfrJOn6b78+p4RR49qMAksc6Q=; b=cKEKx1CPNGcOEV5NPJR6A2AjOTNNOszyjxqRez4Cz7V6/zsZGtTTf2/rJBATrg8DwvYvwScZ2nJV0/EUdWD3gp4+tWS9ma/R70/3hWwtzvv1CMK4OFi5hlRqcQOxcuydzKDTyhIEA5lugilUOqZZRbwfkegfzDNmQrZwgICYgkA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172009547097483.317160470359; Thu, 4 Jul 2024 05:17:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPLOu-0008Gw-W7; Thu, 04 Jul 2024 08:17:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPLNu-0007tY-Hx for qemu-devel@nongnu.org; Thu, 04 Jul 2024 08:16:30 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sPLNc-0002R3-1G for qemu-devel@nongnu.org; Thu, 04 Jul 2024 08:16:21 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-42567ddf099so3756045e9.3 for ; Thu, 04 Jul 2024 05:16:03 -0700 (PDT) Received: from localhost.localdomain (adsl-241.37.6.160.tellas.gr. [37.6.160.241]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a2ca5casm22471015e9.32.2024.07.04.05.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 05:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720095362; x=1720700162; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eoRb5gNelpL+/SZJuMxfrJOn6b78+p4RR49qMAksc6Q=; b=FQniMsxKOvZRnUmCEM0kbe4tXCQxdWn/RC24ajLVh8IJh9EoWS7NgTBkx53d0OZTBx ixcjQikJU8h7tx+luKGIqOCopXcaVMUB5/TygbDdxQwyVa+NRg6qiv4IcE6jSv95sB/H occ02JAx8rywaDhd3EDmHbNcKELDYRiH5ge24v8uVbAeexbCQGctHYBCYzEKPEvXpsXf LOPN8G/oFVCyiAGx/+KK8X16NLT9ZWjjz9X0NQ2y47xT9+FBLV0dvSHCDg70Na6Sh9gM /ox1JAR14X//2LYs3C67IfugBDLqAUOU+63G8yvKFkt+/kxiOB0JXflo1sVuqM9O39dY se/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720095362; x=1720700162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eoRb5gNelpL+/SZJuMxfrJOn6b78+p4RR49qMAksc6Q=; b=GIVndDQJDzZzAnnJRUHj1qbNUcPT9/OncJmh334RyNS20HOoODdDP+lgz0L6/wAD0s RWNAwImQpGpUV7zYf+pCIv39Oig8BUsUgQ35vCCPUAbqQ1lB+Nqfl80i9uat51HgiLjH 76W+A4osxGLqSiTTCjbrVuJOyfU66aJtkkyftqQ5nwe6PmDR07blm8W57PPYeMoOyycN meOkgUyLJINAYS2liHIGWgXain8L9ALS3NtKk7Wp8VmihPHpBZLcGZsEo4nz+Gmj4vIM Qe5KX4kmssfNzIWkvKlA2ySFwQL1/YlRKmYuJ3dlbWhwy6iynn/bUDVzteB61st6w3Em QQPg== X-Gm-Message-State: AOJu0YyXNHljfp4CEbpcFvoYO0T/A/snggKNYOj7aUDdiaf8kGrm5Doq ZAX4eDzPj2WGzsD1uWM4pQ4q9VdHHtgn40snbI4o858/W4TQu+fnG6sa4ffasYf1itutw4gnUry l7oY= X-Google-Smtp-Source: AGHT+IEawnden7sYBYyRupYBypwaBsXLukkF2UMkFjog8ihUin7kt8YBIsZnxH1+Ri3akQ5XgHDPKQ== X-Received: by 2002:a05:600c:364c:b0:425:7a99:e6f2 with SMTP id 5b1f17b1804b1-4264a3e31bfmr13021295e9.14.1720095361724; Thu, 04 Jul 2024 05:16:01 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson Subject: [RFC PATCH v4 3/7] rust: add crate to expose bindings and interfaces Date: Thu, 4 Jul 2024 15:15:39 +0300 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720095472560100003 Content-Type: text/plain; charset="utf-8" Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and provides some declaration macros for symbols visible to the rest of QEMU. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 7 ++ rust/.cargo/config.toml | 2 + rust/qemu-api/.gitignore | 2 + rust/qemu-api/Cargo.lock | 7 ++ rust/qemu-api/Cargo.toml | 59 ++++++++++++++ rust/qemu-api/README.md | 17 ++++ rust/qemu-api/build.rs | 48 +++++++++++ rust/qemu-api/deny.toml | 57 +++++++++++++ rust/qemu-api/meson.build | 0 rust/qemu-api/rustfmt.toml | 1 + rust/qemu-api/src/bindings.rs | 8 ++ rust/qemu-api/src/definitions.rs | 112 +++++++++++++++++++++++++ rust/qemu-api/src/device_class.rs | 131 ++++++++++++++++++++++++++++++ rust/qemu-api/src/lib.rs | 29 +++++++ rust/qemu-api/src/tests.rs | 48 +++++++++++ rust/rustfmt.toml | 7 ++ 16 files changed, 535 insertions(+) create mode 100644 rust/.cargo/config.toml create mode 100644 rust/qemu-api/.gitignore create mode 100644 rust/qemu-api/Cargo.lock create mode 100644 rust/qemu-api/Cargo.toml create mode 100644 rust/qemu-api/README.md create mode 100644 rust/qemu-api/build.rs create mode 100644 rust/qemu-api/deny.toml create mode 100644 rust/qemu-api/meson.build create mode 120000 rust/qemu-api/rustfmt.toml create mode 100644 rust/qemu-api/src/bindings.rs create mode 100644 rust/qemu-api/src/definitions.rs create mode 100644 rust/qemu-api/src/device_class.rs create mode 100644 rust/qemu-api/src/lib.rs create mode 100644 rust/qemu-api/src/tests.rs create mode 100644 rust/rustfmt.toml diff --git a/MAINTAINERS b/MAINTAINERS index 6e7b8207fb..8598d38eae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3340,6 +3340,11 @@ F: hw/core/register.c F: include/hw/register.h F: include/hw/registerfields.h =20 +Rust +M: Manos Pitsidianakis +S: Maintained +F: rust/qemu-api + SLIRP M: Samuel Thibault S: Maintained @@ -4233,6 +4238,8 @@ F: scripts/cargo_wrapper.py F: rust/meson.build F: rust/wrapper.h F: rust/.gitignore +F: rust/rustfmt.toml +F: rust/.cargo/config.toml =20 Miscellaneous ------------- diff --git a/rust/.cargo/config.toml b/rust/.cargo/config.toml new file mode 100644 index 0000000000..241210ffa7 --- /dev/null +++ b/rust/.cargo/config.toml @@ -0,0 +1,2 @@ +[build] +rustflags =3D ["-Crelocation-model=3Dpic", "-Ctarget-feature=3D+crt-static= "] diff --git a/rust/qemu-api/.gitignore b/rust/qemu-api/.gitignore new file mode 100644 index 0000000000..71eaff2035 --- /dev/null +++ b/rust/qemu-api/.gitignore @@ -0,0 +1,2 @@ +# Ignore generated bindings file overrides. +src/bindings.rs.inc diff --git a/rust/qemu-api/Cargo.lock b/rust/qemu-api/Cargo.lock new file mode 100644 index 0000000000..e9c51a243a --- /dev/null +++ b/rust/qemu-api/Cargo.lock @@ -0,0 +1,7 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version =3D 3 + +[[package]] +name =3D "qemu_api" +version =3D "0.1.0" diff --git a/rust/qemu-api/Cargo.toml b/rust/qemu-api/Cargo.toml new file mode 100644 index 0000000000..94a48b9ce9 --- /dev/null +++ b/rust/qemu-api/Cargo.toml @@ -0,0 +1,59 @@ +[package] +name =3D "qemu_api" +version =3D "0.1.0" +edition =3D "2021" +authors =3D ["Manos Pitsidianakis "] +license =3D "GPL-2.0 OR GPL-3.0-or-later" +readme =3D "README.md" +homepage =3D "https://www.qemu.org" +description =3D "Rust bindings for QEMU" +repository =3D "https://gitlab.com/epilys/rust-for-qemu" +resolver =3D "2" +publish =3D false +keywords =3D [] +categories =3D [] + +[dependencies] + +[lints] +[lints.rustdoc] +broken_intra_doc_links =3D "deny" +redundant_explicit_links =3D "deny" +[lints.clippy] +# lint groups +correctness =3D { level =3D "deny", priority =3D -1 } +suspicious =3D { level =3D "deny", priority =3D -1 } +complexity =3D { level =3D "deny", priority =3D -1 } +perf =3D { level =3D "deny", priority =3D -1 } +cargo =3D { level =3D "deny", priority =3D -1 } +nursery =3D { level =3D "deny", priority =3D -1 } +style =3D { level =3D "deny", priority =3D -1 } +# restriction group +dbg_macro =3D "deny" +rc_buffer =3D "deny" +as_underscore =3D "deny" +assertions_on_result_states =3D "deny" +# pedantic group +doc_markdown =3D "deny" +expect_fun_call =3D "deny" +borrow_as_ptr =3D "deny" +case_sensitive_file_extension_comparisons =3D "deny" +cast_lossless =3D "deny" +cast_ptr_alignment =3D "allow" +large_futures =3D "deny" +waker_clone_wake =3D "deny" +unused_enumerate_index =3D "deny" +unnecessary_fallible_conversions =3D "deny" +struct_field_names =3D "deny" +manual_hash_one =3D "deny" +into_iter_without_iter =3D "deny" +option_if_let_else =3D "deny" +missing_const_for_fn =3D "deny" +significant_drop_tightening =3D "deny" +multiple_crate_versions =3D "deny" +significant_drop_in_scrutinee =3D "deny" +cognitive_complexity =3D "deny" +missing_safety_doc =3D "allow" + +# Do not include in any global workspace +[workspace] diff --git a/rust/qemu-api/README.md b/rust/qemu-api/README.md new file mode 100644 index 0000000000..f16a1a929d --- /dev/null +++ b/rust/qemu-api/README.md @@ -0,0 +1,17 @@ +# QEMU bindings and API wrappers + +This library exports helper Rust types, Rust macros and C FFI bindings for= internal QEMU APIs. + +The C bindings can be generated with `bindgen`, using this build target: + +```console +$ ninja bindings-aarch64-softmmu.rs +``` + +## Generate Rust documentation + +To generate docs for this crate, including private items: + +```sh +cargo doc --no-deps --document-private-items +``` diff --git a/rust/qemu-api/build.rs b/rust/qemu-api/build.rs new file mode 100644 index 0000000000..13164f8371 --- /dev/null +++ b/rust/qemu-api/build.rs @@ -0,0 +1,48 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use std::{env, path::Path}; + +fn main() { + println!("cargo:rerun-if-env-changed=3DMESON_BUILD_ROOT"); + println!("cargo:rerun-if-changed=3Dsrc/bindings.rs.inc"); + + let out_dir =3D env::var_os("OUT_DIR").unwrap(); + + if let Some(build_dir) =3D std::env::var_os("MESON_BUILD_ROOT") { + let mut build_dir =3D Path::new(&build_dir).to_path_buf(); + let mut out_dir =3D Path::new(&out_dir).to_path_buf(); + assert!( + build_dir.exists(), + "MESON_BUILD_ROOT value does not exist on filesystem: {}", + build_dir.display() + ); + assert!( + build_dir.is_dir(), + "MESON_BUILD_ROOT value is not actually a directory: {}", + build_dir.display() + ); + // TODO: add logic for other guest target architectures. + build_dir.push("bindings-aarch64-softmmu.rs"); + let bindings_rs =3D build_dir; + assert!( + bindings_rs.exists(), + "MESON_BUILD_ROOT/bindings-aarch64-softmmu.rs does not exist o= n filesystem: {}", + bindings_rs.display() + ); + assert!( + bindings_rs.is_file(), + "MESON_BUILD_ROOT/bindings-aarch64-softmmu.rs is not a file: {= }", + bindings_rs.display() + ); + out_dir.push("bindings.rs"); + std::fs::copy(bindings_rs, out_dir).unwrap(); + println!("cargo:rustc-cfg=3DMESON_BINDINGS_RS"); + } else if !Path::new("src/bindings.rs.inc").exists() { + panic!( + "No generated C bindings found! Either build them manually wit= h bindgen or with meson \ + (`ninja bindings-aarch64-softmmu.rs`) and copy them to src/bi= ndings.rs.inc, or build \ + through meson." + ); + } +} diff --git a/rust/qemu-api/deny.toml b/rust/qemu-api/deny.toml new file mode 100644 index 0000000000..3992380509 --- /dev/null +++ b/rust/qemu-api/deny.toml @@ -0,0 +1,57 @@ +# cargo-deny configuration file + +[graph] +targets =3D [ + "aarch64-unknown-linux-gnu", + "x86_64-unknown-linux-gnu", + "x86_64-apple-darwin", + "aarch64-apple-darwin", + "x86_64-pc-windows-gnu", + "aarch64-pc-windows-gnullvm", +] +#exclude =3D [] +all-features =3D false +no-default-features =3D false +#features =3D [] + +[output] +feature-depth =3D 1 + +[advisories] +db-path =3D "$CARGO_HOME/advisory-dbs" +db-urls =3D ["https://github.com/rustsec/advisory-db"] +ignore =3D [] + +[licenses] +allow =3D [ + "GPL-2.0", + "MIT", + "Apache-2.0", + "Unicode-DFS-2016", +] +confidence-threshold =3D 0.8 +exceptions =3D [] + +[licenses.private] +ignore =3D false +registries =3D [] + +[bans] +multiple-versions =3D "warn" +wildcards =3D "deny" +# The graph highlighting used when creating dotgraphs for crates +# with multiple versions +# * lowest-version - The path to the lowest versioned duplicate is highlig= hted +# * simplest-path - The path to the version with the fewest edges is highl= ighted +# * all - Both lowest-version and simplest-path are used +highlight =3D "all" +workspace-default-features =3D "allow" +external-default-features =3D "allow" +allow =3D [] +deny =3D [] + +[sources] +unknown-registry =3D "deny" +unknown-git =3D "deny" +allow-registry =3D ["https://github.com/rust-lang/crates.io-index"] +allow-git =3D [] diff --git a/rust/qemu-api/meson.build b/rust/qemu-api/meson.build new file mode 100644 index 0000000000..e69de29bb2 diff --git a/rust/qemu-api/rustfmt.toml b/rust/qemu-api/rustfmt.toml new file mode 120000 index 0000000000..39f97b043b --- /dev/null +++ b/rust/qemu-api/rustfmt.toml @@ -0,0 +1 @@ +../rustfmt.toml \ No newline at end of file diff --git a/rust/qemu-api/src/bindings.rs b/rust/qemu-api/src/bindings.rs new file mode 100644 index 0000000000..1220a3d8f0 --- /dev/null +++ b/rust/qemu-api/src/bindings.rs @@ -0,0 +1,8 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +#[cfg(MESON_BINDINGS_RS)] +include!(concat!(env!("OUT_DIR"), "/bindings.rs")); + +#[cfg(not(MESON_BINDINGS_RS))] +include!("bindings.rs.inc"); diff --git a/rust/qemu-api/src/definitions.rs b/rust/qemu-api/src/definitio= ns.rs new file mode 100644 index 0000000000..04b3a4d565 --- /dev/null +++ b/rust/qemu-api/src/definitions.rs @@ -0,0 +1,112 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +//! Definitions required by QEMU when registering a device. + +use crate::bindings::*; + +unsafe impl Sync for TypeInfo {} +unsafe impl Sync for VMStateDescription {} + +#[macro_export] +macro_rules! module_init { + ($func:expr, $type:expr) =3D> { + #[used] + #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] + #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] + #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] + pub static LOAD_MODULE: extern "C" fn() =3D { + assert!($type < $crate::bindings::module_init_type_MODULE_INIT= _MAX); + + extern "C" fn __load() { + // ::std::panic::set_hook(::std::boxed::Box::new(|_| {})); + + unsafe { + $crate::bindings::register_module_init(Some($func), $t= ype); + } + } + + __load + }; + }; + (qom: $func:ident =3D> $body:block) =3D> { + // NOTE: To have custom identifiers for the ctor func we need to e= ither supply + // them directly as a macro argument or create them with a proc ma= cro. + #[used] + #[cfg_attr(target_os =3D "linux", link_section =3D ".ctors")] + #[cfg_attr(target_os =3D "macos", link_section =3D "__DATA,__mod_i= nit_func")] + #[cfg_attr(target_os =3D "windows", link_section =3D ".CRT$XCU")] + pub static LOAD_MODULE: extern "C" fn() =3D { + extern "C" fn __load() { + // ::std::panic::set_hook(::std::boxed::Box::new(|_| {})); + #[no_mangle] + unsafe extern "C" fn $func() { + $body + } + + unsafe { + $crate::bindings::register_module_init( + Some($func), + $crate::bindings::module_init_type_MODULE_INIT_QOM, + ); + } + } + + __load + }; + }; +} + +#[macro_export] +macro_rules! type_info { + ($(#[$outer:meta])* + $name:ident: $t:ty, + $(name: $tname:expr,)* + $(parent: $pname:expr,)* + $(instance_init: $ii_fn:expr,)* + $(instance_post_init: $ipi_fn:expr,)* + $(instance_finalize: $if_fn:expr,)* + $(abstract_: $a_val:expr,)* + $(class_init: $ci_fn:expr,)* + $(class_base_init: $cbi_fn:expr,)* + ) =3D> { + #[used] + $(#[$outer])* + pub static $name: $crate::bindings::TypeInfo =3D $crate::bindings:= :TypeInfo { + $(name: { + #[used] + static TYPE_NAME: &::core::ffi::CStr =3D $tname; + $tname.as_ptr() + },)* + $(parent: { + #[used] + static PARENT_TYPE_NAME: &::core::ffi::CStr =3D $pname; + $pname.as_ptr() + },)* + instance_size: ::core::mem::size_of::<$t>(), + instance_align: ::core::mem::align_of::<$t>(), + $( + instance_init: $ii_fn, + )* + $( + instance_post_init: $ipi_fn, + )* + $( + instance_finalize: $if_fn, + )* + $( + abstract_: $a_val, + )* + class_size: 0, + $( + class_init: $ci_fn, + )* + $( + class_base_init: $cbi_fn, + )* + class_data: core::ptr::null_mut(), + interfaces: core::ptr::null_mut(), + ..unsafe { MaybeUninit::<$crate::bindings::TypeInfo>::zeroed()= .assume_init() } + }; + } +} diff --git a/rust/qemu-api/src/device_class.rs b/rust/qemu-api/src/device_c= lass.rs new file mode 100644 index 0000000000..855d70364a --- /dev/null +++ b/rust/qemu-api/src/device_class.rs @@ -0,0 +1,131 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use std::sync::OnceLock; + +use crate::bindings::*; + +unsafe impl Send for Property {} +unsafe impl Sync for Property {} + +#[macro_export] +macro_rules! device_class_init { + ($func:ident, props =3D> $props:ident, realize_fn =3D> $realize_fn:exp= r, reset_fn =3D> $reset_fn:expr, vmsd =3D> $vmsd:ident$(,)*) =3D> { + #[no_mangle] + pub unsafe extern "C" fn $func( + klass: *mut $crate::bindings::ObjectClass, + _: *mut ::core::ffi::c_void, + ) { + let mut dc =3D + ::core::ptr::NonNull::new(klass.cast::<$crate::bindings::D= eviceClass>()).unwrap(); + dc.as_mut().realize =3D $realize_fn; + dc.as_mut().reset =3D $reset_fn; + dc.as_mut().vmsd =3D &$vmsd; + $crate::bindings::device_class_set_props(dc.as_mut(), $props.a= s_mut_ptr()); + } + }; +} + +#[macro_export] +macro_rules! define_property { + ($name:expr, $state:ty, $field:expr, $prop:expr, $type:expr, default = =3D $defval:expr$(,)*) =3D> { + $crate::bindings::Property { + name: { + #[used] + static _TEMP: &::core::ffi::CStr =3D $name; + _TEMP.as_ptr() + }, + info: $prop, + offset: ::core::mem::offset_of!($state, $field) + .try_into() + .expect("Could not fit offset value to type"), + bitnr: 0, + bitmask: 0, + set_default: true, + defval: $crate::bindings::Property__bindgen_ty_1 { u: $defval.= into() }, + arrayoffset: 0, + arrayinfo: ::core::ptr::null(), + arrayfieldsize: 0, + link_type: ::core::ptr::null(), + } + }; + ($name:expr, $state:ty, $field:expr, $prop:expr, $type:expr$(,)*) =3D>= { + $crate::bindings::Property { + name: { + #[used] + static _TEMP: &::core::ffi::CStr =3D $name; + _TEMP.as_ptr() + }, + info: $prop, + offset: ::core::mem::offset_of!($state, $field) + .try_into() + .expect("Could not fit offset value to type"), + bitnr: 0, + bitmask: 0, + set_default: false, + defval: $crate::bindings::Property__bindgen_ty_1 { i: 0 }, + arrayoffset: 0, + arrayinfo: ::core::ptr::null(), + arrayfieldsize: 0, + link_type: ::core::ptr::null(), + } + }; +} + +#[repr(C)] +pub struct Properties(pub OnceLock<[Property; N]>, pub fn(= ) -> [Property; N]); + +impl Properties { + pub unsafe fn as_mut_ptr(&mut self) -> *mut Property { + _ =3D self.0.get_or_init(self.1); + self.0.get_mut().unwrap().as_mut_ptr() + } +} + +#[macro_export] +macro_rules! declare_properties { + ($ident:ident, $($prop:expr),*$(,)*) =3D> { + + const fn _calc_prop_len() -> usize { + let mut len =3D 1; + $({ + _ =3D stringify!($prop); + len +=3D 1; + })* + len + } + const PROP_LEN: usize =3D _calc_prop_len(); + + #[no_mangle] + fn _make_properties() -> [$crate::bindings::Property; PROP_LEN] { + [ + $($prop),*, + unsafe { ::core::mem::MaybeUninit::<$crate::bindings::= Property>::zeroed().assume_init() }, + ] + } + + #[no_mangle] + pub static mut $ident: $crate::device_class::Properties = =3D $crate::device_class::Properties(::std::sync::OnceLock::new(), _make_pr= operties); + }; +} + +#[macro_export] +macro_rules! vm_state_description { + ($(#[$outer:meta])* + $name:ident, + $(name: $vname:expr,)* + $(unmigratable: $um_val:expr,)* + ) =3D> { + #[used] + $(#[$outer])* + pub static $name: $crate::bindings::VMStateDescription =3D $crate:= :bindings::VMStateDescription { + $(name: { + #[used] + static VMSTATE_NAME: &::core::ffi::CStr =3D $vname; + $vname.as_ptr() + },)* + unmigratable: true, + ..unsafe { ::core::mem::MaybeUninit::<$crate::bindings::VMStat= eDescription>::zeroed().assume_init() } + }; + } +} diff --git a/rust/qemu-api/src/lib.rs b/rust/qemu-api/src/lib.rs new file mode 100644 index 0000000000..74825c84e7 --- /dev/null +++ b/rust/qemu-api/src/lib.rs @@ -0,0 +1,29 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +#![doc =3D include_str!("../README.md")] + +// FIXME: remove improper_ctypes +#[allow( + improper_ctypes_definitions, + improper_ctypes, + non_camel_case_types, + non_snake_case, + non_upper_case_globals +)] +#[allow( + clippy::missing_const_for_fn, + clippy::useless_transmute, + clippy::too_many_arguments, + clippy::approx_constant, + clippy::use_self, + clippy::cast_lossless, +)] +#[rustfmt::skip] +pub mod bindings; + +pub mod definitions; +pub mod device_class; + +#[cfg(test)] +mod tests; diff --git a/rust/qemu-api/src/tests.rs b/rust/qemu-api/src/tests.rs new file mode 100644 index 0000000000..88c26308ee --- /dev/null +++ b/rust/qemu-api/src/tests.rs @@ -0,0 +1,48 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use crate::{ + bindings::*, declare_properties, define_property, device_class_init, v= m_state_description, +}; + +#[test] +fn test_device_decl_macros() { + // Test that macros can compile. + vm_state_description! { + VMSTATE, + name: c"name", + unmigratable: true, + } + + #[repr(C)] + pub struct DummyState { + pub char_backend: CharBackend, + pub migrate_clock: bool, + } + + declare_properties! { + DUMMY_PROPERTIES, + define_property!( + c"chardev", + DummyState, + char_backend, + unsafe { &qdev_prop_chr }, + CharBackend + ), + define_property!( + c"migrate-clk", + DummyState, + migrate_clock, + unsafe { &qdev_prop_bool }, + bool + ), + } + + device_class_init! { + dummy_class_init, + props =3D> DUMMY_PROPERTIES, + realize_fn =3D> None, + reset_fn =3D> None, + vmsd =3D> VMSTATE, + } +} diff --git a/rust/rustfmt.toml b/rust/rustfmt.toml new file mode 100644 index 0000000000..ebecb99fe0 --- /dev/null +++ b/rust/rustfmt.toml @@ -0,0 +1,7 @@ +edition =3D "2021" +format_generated_files =3D false +format_code_in_doc_comments =3D true +format_strings =3D true +imports_granularity =3D "Crate" +group_imports =3D "StdExternalCrate" +wrap_comments =3D true --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89 From nobody Sun Nov 24 20:49:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1720095454; cv=none; d=zohomail.com; s=zohoarc; b=OBeM2OiCiwo3TajG9mqREa8SyADhL7fevpli8o6jPDkdPy6KoKm1iwbIUYladm9CjOZaVnWvUgQc3LwlzaQwg6V8pxqIfhJLfhTr3QfiCIlnLozvtWFE2vJdX1r6MIg5mF7//uh4NROlj08+2cvVLr6tQHRhNb+pPVCeakjIkY0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720095454; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=llrJ0fioMvZ2Dz1eTwAi014ZiA1w9XkdIPsyaQw1FxU=; b=nuU/HLlUoAbEkegPz1a8pKirXNEn7q4fGLmMd7QCLbO/X33FmdiqdWZvvEYzZbQXIIb41a8Kc/iqWnV8dCn1SwyokzUHXCMgMMgc87COXcAtJ44jSiVe+TEnQcH24d2nUy54RDBayEsZBunjV2yF0jEfvJV1cguNKLDjK9z2axE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720095454599406.19404194954313; Thu, 4 Jul 2024 05:17:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPLOz-0008Vr-Uo; Thu, 04 Jul 2024 08:17:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPLOC-0007vX-Fn for qemu-devel@nongnu.org; Thu, 04 Jul 2024 08:16:41 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sPLNg-0002RQ-My for qemu-devel@nongnu.org; Thu, 04 Jul 2024 08:16:23 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4264a3847b6so3889795e9.0 for ; Thu, 04 Jul 2024 05:16:06 -0700 (PDT) Received: from localhost.localdomain (adsl-241.37.6.160.tellas.gr. [37.6.160.241]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a2ca5casm22471015e9.32.2024.07.04.05.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 05:16:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720095365; x=1720700165; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=llrJ0fioMvZ2Dz1eTwAi014ZiA1w9XkdIPsyaQw1FxU=; b=HqOZ0JbhsSG7oG+VWtKDX9otRjuX0aJe1gA3eJY/SHZ4cZyqp5A2kioGy1m6qguAFo i9UzbQi0u/zYNl8XnlK/j24HhGdHBHJSlqL9wSVeprpWyKnsO9XkTIMtz3QwFh3rcKy0 O7sX+xkvL4FyOnoqfhKe6CKcHn/DK1mYGQA1EHq4jimrRQMUKRQDXGh81ZWJWP0FplMU aGOuxS1vXFkYmNTbnOLdQ6BVKdzLCUgZltd7AEPxkYk7JpxoUGaNf8FWui07QKsuYjFX g6zM7NLea2TM09D3QpyghXR/LdFY4I3NC1HxhY/nObDprV0mbEJ+8K6SEC9tJRNrxX4m WsVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720095365; x=1720700165; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=llrJ0fioMvZ2Dz1eTwAi014ZiA1w9XkdIPsyaQw1FxU=; b=GoYfkxN5hhtxHqlMdiztmmhTJlRo4/mq5C8rw4pwTWRrJNXkALQ18hZwrYjo/+lZ2A 36jA39E26ZIzj7G91QjWQQPG7wbczSE5MyDMc1T//InLZDDn6sV9FP8YIcomzi9Cv09C Vyt7ox7Uml9gHwkC/4FsaMwmdyLR3xf9s5G0aiAKgX656CdDqj4YHIeBuTdkbSQmMG6p 2tCLMMIhhphbb62k0ciR+Qfx7VZVpnpOHPtp1IAjkHgkwtHtmdQOMDDk6JdJexFtVnHE Mtn14dVb/6hO7mVFViwJkqcrX1QqQFdf7Hip77FvY7fQAZg9DRJyturAYV2CVsTKU4xw B2Lg== X-Gm-Message-State: AOJu0Yy3sTA6ajPlk1dHID4sD4+uuMrTR5Z2OhyneM7NGOhe7lleUqoG CSbOaD7frpu5ufzou4GrxV+IHZdAlqNqwWmX6jIX5CCGT9h0wOThmS+PbS90OIpmTsCwumkwwfg DDsg= X-Google-Smtp-Source: AGHT+IH82NCyVSt8c068S8QWbQVsJHz6DtwE2K7mP3JYLpr1Uz5fDaL9zfTrorZXV7nAd6YfHocNng== X-Received: by 2002:a05:600c:4da2:b0:425:77ad:93cb with SMTP id 5b1f17b1804b1-4264a3cc8b0mr9943445e9.2.1720095364721; Thu, 04 Jul 2024 05:16:04 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson , Paolo Bonzini Subject: [RFC PATCH v4 4/7] rust: add PL011 device model Date: Thu, 4 Jul 2024 15:15:40 +0300 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720095456495100013 Content-Type: text/plain; charset="utf-8" This commit adds a re-implementation of hw/char/pl011.c in Rust. How to build: 1. Make sure rust, cargo and bindgen (cargo install bindgen-cli) are installed 2. Configure a QEMU build with: --enable-system --target-list=3Daarch64-softmmu --enable-with-rust 3. Launching a VM with qemu-system-aarch64 should use the Rust version of the pl011 device (unless it is not set up so in hw/arm/virt.c; the type of the UART device is hardcoded). To confirm, inspect `info qom-tree` in the monitor and look for an `x-pl011-rust` device. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 5 + meson.build | 4 + rust/meson.build | 2 + rust/pl011/.gitignore | 2 + rust/pl011/Cargo.lock | 125 ++++++++ rust/pl011/Cargo.toml | 67 ++++ rust/pl011/README.md | 31 ++ rust/pl011/deny.toml | 57 ++++ rust/pl011/meson.build | 7 + rust/pl011/rustfmt.toml | 1 + rust/pl011/src/definitions.rs | 39 +++ rust/pl011/src/device.rs | 509 ++++++++++++++++++++++++++++++ rust/pl011/src/device_class.rs | 48 +++ rust/pl011/src/lib.rs | 556 +++++++++++++++++++++++++++++++++ rust/pl011/src/memory_ops.rs | 45 +++ 15 files changed, 1498 insertions(+) create mode 100644 rust/pl011/.gitignore create mode 100644 rust/pl011/Cargo.lock create mode 100644 rust/pl011/Cargo.toml create mode 100644 rust/pl011/README.md create mode 100644 rust/pl011/deny.toml create mode 100644 rust/pl011/meson.build create mode 120000 rust/pl011/rustfmt.toml create mode 100644 rust/pl011/src/definitions.rs create mode 100644 rust/pl011/src/device.rs create mode 100644 rust/pl011/src/device_class.rs create mode 100644 rust/pl011/src/lib.rs create mode 100644 rust/pl011/src/memory_ops.rs diff --git a/MAINTAINERS b/MAINTAINERS index 8598d38eae..fedee0ddef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1186,6 +1186,11 @@ F: include/hw/*/microbit*.h F: tests/qtest/microbit-test.c F: docs/system/arm/nrf.rst =20 +ARM PL011 Rust device +M: Manos Pitsidianakis +S: Maintained +F: rust/pl011/ + AVR Machines ------------- =20 diff --git a/meson.build b/meson.build index 71011fd3b3..945ce6aaaf 100644 --- a/meson.build +++ b/meson.build @@ -296,6 +296,10 @@ if get_option('with_rust').allowed() endif with_rust =3D cargo.found() =20 +if with_rust + subdir('rust') +endif + # default flags for all hosts # We use -fwrapv to tell the compiler that we require a C dialect where # left shift of signed integers is well defined and has the expected diff --git a/rust/meson.build b/rust/meson.build index 5fdc2621a3..21115ac56d 100644 --- a/rust/meson.build +++ b/rust/meson.build @@ -93,6 +93,8 @@ subdir('qemu-api') # bindgen dependency is declared. rust_hw_target_list =3D {} =20 +subdir('pl011') + foreach rust_hw_target, rust_hws: rust_hw_target_list foreach rust_hw_dev: rust_hws crate_metadata =3D { diff --git a/rust/pl011/.gitignore b/rust/pl011/.gitignore new file mode 100644 index 0000000000..71eaff2035 --- /dev/null +++ b/rust/pl011/.gitignore @@ -0,0 +1,2 @@ +# Ignore generated bindings file overrides. +src/bindings.rs.inc diff --git a/rust/pl011/Cargo.lock b/rust/pl011/Cargo.lock new file mode 100644 index 0000000000..411bfed9c9 --- /dev/null +++ b/rust/pl011/Cargo.lock @@ -0,0 +1,125 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version =3D 3 + +[[package]] +name =3D "arbitrary-int" +version =3D "1.2.7" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c84fc003e338a6f69fbd4f7fe9f92b535ff13e9af8997f3b14b6ddff8b1d= f46d" + +[[package]] +name =3D "bilge" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "dc707ed8ebf81de5cd6c7f48f54b4c8621760926cdf35a57000747c512e6= 7b57" +dependencies =3D [ + "arbitrary-int", + "bilge-impl", +] + +[[package]] +name =3D "bilge-impl" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "feb11e002038ad243af39c2068c8a72bcf147acf05025dcdb916fcc000ad= b2d8" +dependencies =3D [ + "itertools", + "proc-macro-error", + "proc-macro2", + "quote", + "syn", +] + +[[package]] +name =3D "either" +version =3D "1.12.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "3dca9240753cf90908d7e4aac30f630662b02aebaa1b58a3cadabdb23385= b58b" + +[[package]] +name =3D "itertools" +version =3D "0.11.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "b1c173a5686ce8bfa551b3563d0c2170bf24ca44da99c7ca4bfdab5418c3= fe57" +dependencies =3D [ + "either", +] + +[[package]] +name =3D "pl011" +version =3D "0.1.0" +dependencies =3D [ + "arbitrary-int", + "bilge", + "bilge-impl", + "qemu_api", +] + +[[package]] +name =3D "proc-macro-error" +version =3D "1.0.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "da25490ff9892aab3fcf7c36f08cfb902dd3e71ca0f9f9517bea02a73a5c= e38c" +dependencies =3D [ + "proc-macro-error-attr", + "proc-macro2", + "quote", + "version_check", +] + +[[package]] +name =3D "proc-macro-error-attr" +version =3D "1.0.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "a1be40180e52ecc98ad80b184934baf3d0d29f979574e439af5a55274b35= f869" +dependencies =3D [ + "proc-macro2", + "quote", + "version_check", +] + +[[package]] +name =3D "proc-macro2" +version =3D "1.0.84" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "ec96c6a92621310b51366f1e28d05ef11489516e93be030060e5fc12024a= 49d6" +dependencies =3D [ + "unicode-ident", +] + +[[package]] +name =3D "qemu_api" +version =3D "0.1.0" + +[[package]] +name =3D "quote" +version =3D "1.0.36" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "0fa76aaf39101c457836aec0ce2316dbdc3ab723cdda1c6bd4e6ad4208ac= aca7" +dependencies =3D [ + "proc-macro2", +] + +[[package]] +name =3D "syn" +version =3D "2.0.66" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cd= cff5" +dependencies =3D [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name =3D "unicode-ident" +version =3D "1.0.12" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0f= ee4b" + +[[package]] +name =3D "version_check" +version =3D "0.9.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e= 483f" diff --git a/rust/pl011/Cargo.toml b/rust/pl011/Cargo.toml new file mode 100644 index 0000000000..51f672d883 --- /dev/null +++ b/rust/pl011/Cargo.toml @@ -0,0 +1,67 @@ +[package] +name =3D "pl011" +version =3D "0.1.0" +edition =3D "2021" +authors =3D ["Manos Pitsidianakis "] +license =3D "GPL-2.0 OR GPL-3.0-or-later" +readme =3D "README.md" +homepage =3D "https://www.qemu.org" +description =3D "pl011 device model for QEMU" +repository =3D "https://gitlab.com/epilys/rust-for-qemu" +resolver =3D "2" +publish =3D false +keywords =3D [] +categories =3D [] + +[lib] +crate-type =3D ["staticlib"] + +# bilge deps included here to include them with docs +[dependencies] +arbitrary-int =3D { version =3D "1.2.7" } +bilge =3D { version =3D "0.2.0" } +bilge-impl =3D { version =3D "0.2.0" } +qemu_api =3D { path =3D "../qemu-api" } + +[lints] +[lints.rustdoc] +broken_intra_doc_links =3D "deny" +redundant_explicit_links =3D "deny" +[lints.clippy] +# lint groups +correctness =3D { level =3D "deny", priority =3D -1 } +suspicious =3D { level =3D "deny", priority =3D -1 } +complexity =3D { level =3D "deny", priority =3D -1 } +perf =3D { level =3D "deny", priority =3D -1 } +cargo =3D { level =3D "deny", priority =3D -1 } +nursery =3D { level =3D "deny", priority =3D -1 } +style =3D { level =3D "deny", priority =3D -1 } +# restriction group +dbg_macro =3D "deny" +rc_buffer =3D "deny" +as_underscore =3D "deny" +assertions_on_result_states =3D "deny" +# pedantic group +doc_markdown =3D "deny" +expect_fun_call =3D "deny" +borrow_as_ptr =3D "deny" +case_sensitive_file_extension_comparisons =3D "deny" +cast_lossless =3D "deny" +cast_ptr_alignment =3D "allow" +large_futures =3D "deny" +waker_clone_wake =3D "deny" +unused_enumerate_index =3D "deny" +unnecessary_fallible_conversions =3D "deny" +struct_field_names =3D "deny" +manual_hash_one =3D "deny" +into_iter_without_iter =3D "deny" +option_if_let_else =3D "deny" +missing_const_for_fn =3D "deny" +significant_drop_tightening =3D "deny" +multiple_crate_versions =3D "deny" +significant_drop_in_scrutinee =3D "deny" +cognitive_complexity =3D "deny" +missing_safety_doc =3D "allow" + +# Do not include in any global workspace +[workspace] diff --git a/rust/pl011/README.md b/rust/pl011/README.md new file mode 100644 index 0000000000..cd7dea3163 --- /dev/null +++ b/rust/pl011/README.md @@ -0,0 +1,31 @@ +# PL011 QEMU Device Model + +This library implements a device model for the PrimeCell=C2=AE UART (PL011) +device in QEMU. + +## Build static lib + +Host build target must be explicitly specified: + +```sh +cargo build --target x86_64-unknown-linux-gnu +``` + +Replace host target triplet if necessary. + +## Generate Rust documentation + +To generate docs for this crate, including private items: + +```sh +cargo doc --no-deps --document-private-items --target x86_64-unknown-linux= -gnu +``` + +To include direct dependencies like `bilge` (bitmaps for register types): + +```sh +cargo tree --depth 1 -e normal --prefix none \ + | cut -d' ' -f1 \ + | xargs printf -- '-p %s\n' \ + | xargs cargo doc --no-deps --document-private-items --target x86_64-unkn= own-linux-gnu +``` diff --git a/rust/pl011/deny.toml b/rust/pl011/deny.toml new file mode 100644 index 0000000000..3992380509 --- /dev/null +++ b/rust/pl011/deny.toml @@ -0,0 +1,57 @@ +# cargo-deny configuration file + +[graph] +targets =3D [ + "aarch64-unknown-linux-gnu", + "x86_64-unknown-linux-gnu", + "x86_64-apple-darwin", + "aarch64-apple-darwin", + "x86_64-pc-windows-gnu", + "aarch64-pc-windows-gnullvm", +] +#exclude =3D [] +all-features =3D false +no-default-features =3D false +#features =3D [] + +[output] +feature-depth =3D 1 + +[advisories] +db-path =3D "$CARGO_HOME/advisory-dbs" +db-urls =3D ["https://github.com/rustsec/advisory-db"] +ignore =3D [] + +[licenses] +allow =3D [ + "GPL-2.0", + "MIT", + "Apache-2.0", + "Unicode-DFS-2016", +] +confidence-threshold =3D 0.8 +exceptions =3D [] + +[licenses.private] +ignore =3D false +registries =3D [] + +[bans] +multiple-versions =3D "warn" +wildcards =3D "deny" +# The graph highlighting used when creating dotgraphs for crates +# with multiple versions +# * lowest-version - The path to the lowest versioned duplicate is highlig= hted +# * simplest-path - The path to the version with the fewest edges is highl= ighted +# * all - Both lowest-version and simplest-path are used +highlight =3D "all" +workspace-default-features =3D "allow" +external-default-features =3D "allow" +allow =3D [] +deny =3D [] + +[sources] +unknown-registry =3D "deny" +unknown-git =3D "deny" +allow-registry =3D ["https://github.com/rust-lang/crates.io-index"] +allow-git =3D [] diff --git a/rust/pl011/meson.build b/rust/pl011/meson.build new file mode 100644 index 0000000000..cbac0fd94d --- /dev/null +++ b/rust/pl011/meson.build @@ -0,0 +1,7 @@ +rust_pl011 =3D { + 'name': 'pl011', + 'dirname': 'pl011', + 'output': 'libpl011.a', + } + +rust_hw_target_list +=3D {'aarch64-softmmu': [rust_pl011]} diff --git a/rust/pl011/rustfmt.toml b/rust/pl011/rustfmt.toml new file mode 120000 index 0000000000..39f97b043b --- /dev/null +++ b/rust/pl011/rustfmt.toml @@ -0,0 +1 @@ +../rustfmt.toml \ No newline at end of file diff --git a/rust/pl011/src/definitions.rs b/rust/pl011/src/definitions.rs new file mode 100644 index 0000000000..5efe8ae7f0 --- /dev/null +++ b/rust/pl011/src/definitions.rs @@ -0,0 +1,39 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +//! Definitions required by QEMU when registering the device. + +use core::{mem::MaybeUninit, ptr::NonNull}; + +use qemu_api::bindings::*; + +use crate::{device::PL011State, device_class::pl011_class_init}; + +qemu_api::type_info! { + PL011_ARM_INFO: PL011State, + name: c"x-pl011-rust", + parent: TYPE_SYS_BUS_DEVICE, + instance_init: Some(pl011_init), + abstract_: false, + class_init: Some(pl011_class_init), +} + +#[used] +pub static VMSTATE_PL011: VMStateDescription =3D VMStateDescription { + name: PL011_ARM_INFO.name, + unmigratable: true, + ..unsafe { MaybeUninit::::zeroed().assume_init() } +}; + +#[no_mangle] +pub unsafe extern "C" fn pl011_init(obj: *mut Object) { + assert!(!obj.is_null()); + let mut state =3D NonNull::new_unchecked(obj.cast::()); + state.as_mut().init(); +} + +qemu_api::module_init! { + qom: register_type =3D> { + type_register_static(&PL011_ARM_INFO); + } +} diff --git a/rust/pl011/src/device.rs b/rust/pl011/src/device.rs new file mode 100644 index 0000000000..4aedd9582d --- /dev/null +++ b/rust/pl011/src/device.rs @@ -0,0 +1,509 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use core::{ + ffi::{c_int, c_uchar, c_uint, c_void, CStr}, + ptr::{addr_of, addr_of_mut, NonNull}, +}; + +use qemu_api::bindings::{self, *}; + +use crate::{ + definitions::PL011_ARM_INFO, + memory_ops::PL011_OPS, + registers::{self, Interrupt}, + RegisterOffset, +}; + +static PL011_ID_ARM: [c_uchar; 8] =3D [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0,= 0x05, 0xb1]; + +const DATA_BREAK: u32 =3D 1 << 10; + +/// QEMU sourced constant. +pub const PL011_FIFO_DEPTH: usize =3D 16_usize; + +#[repr(C)] +#[derive(Debug)] +/// PL011 Device Model in QEMU +pub struct PL011State { + pub parent_obj: SysBusDevice, + pub iomem: MemoryRegion, + pub readbuff: u32, + #[doc(alias =3D "fr")] + pub flags: registers::Flags, + #[doc(alias =3D "lcr")] + pub line_control: registers::LineControl, + #[doc(alias =3D "rsr")] + pub receive_status_error_clear: registers::ReceiveStatusErrorClear, + #[doc(alias =3D "cr")] + pub control: registers::Control, + pub dmacr: u32, + pub int_enabled: u32, + pub int_level: u32, + pub read_fifo: [u32; PL011_FIFO_DEPTH], + pub ilpr: u32, + pub ibrd: u32, + pub fbrd: u32, + pub ifl: u32, + pub read_pos: usize, + pub read_count: usize, + pub read_trigger: usize, + #[doc(alias =3D "chr")] + pub char_backend: CharBackend, + /// QEMU interrupts + /// + /// ```text + /// * sysbus MMIO region 0: device registers + /// * sysbus IRQ 0: `UARTINTR` (combined interrupt line) + /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line) + /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line) + /// * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line) + /// * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line) + /// * sysbus IRQ 5: `UARTEINTR` (error interrupt line) + /// ``` + #[doc(alias =3D "irq")] + pub interrupts: [qemu_irq; 6usize], + #[doc(alias =3D "clk")] + pub clock: NonNull, + #[doc(alias =3D "migrate_clk")] + pub migrate_clock: bool, +} + +#[used] +pub static CLK_NAME: &CStr =3D c"clk"; + +impl PL011State { + pub fn init(&mut self) { + unsafe { + memory_region_init_io( + addr_of_mut!(self.iomem), + addr_of_mut!(*self).cast::(), + &PL011_OPS, + addr_of_mut!(*self).cast::(), + PL011_ARM_INFO.name, + 0x1000, + ); + let sbd =3D addr_of_mut!(*self).cast::(); + let dev =3D addr_of_mut!(*self).cast::(); + sysbus_init_mmio(sbd, addr_of_mut!(self.iomem)); + for irq in self.interrupts.iter_mut() { + sysbus_init_irq(sbd, irq); + } + self.clock =3D NonNull::new(qdev_init_clock_in( + dev, + CLK_NAME.as_ptr(), + None, /* pl011_clock_update */ + addr_of_mut!(*self).cast::(), + ClockEvent_ClockUpdate, + )) + .unwrap(); + } + } + + pub fn read(&mut self, offset: hwaddr, _size: core::ffi::c_uint) -> u6= 4 { + use RegisterOffset::*; + + match RegisterOffset::try_from(offset) { + Err(v) if (0x3f8..0x400).contains(&v) =3D> { + u64::from(PL011_ID_ARM[((offset - 0xfe0) >> 2) as usize]) + } + Err(_) =3D> { + // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); + 0 + } + Ok(DR) =3D> { + // s->flags &=3D ~PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(false); + let c =3D self.read_fifo[self.read_pos]; + if self.read_count > 0 { + self.read_count -=3D 1; + self.read_pos =3D (self.read_pos + 1) & (self.fifo_dep= th() - 1); + } + if self.read_count =3D=3D 0 { + // self.flags |=3D PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(true); + } + if self.read_count + 1 =3D=3D self.read_trigger { + //self.int_level &=3D ~ INT_RX; + self.int_level &=3D !registers::INT_RX; + } + // Update error bits. + self.receive_status_error_clear =3D c.to_be_bytes()[3].int= o(); + self.update(); + unsafe { qemu_chr_fe_accept_input(&mut self.char_backend) = }; + c.into() + } + Ok(RSR) =3D> u8::from(self.receive_status_error_clear).into(), + Ok(FR) =3D> u16::from(self.flags).into(), + Ok(FBRD) =3D> self.fbrd.into(), + Ok(ILPR) =3D> self.ilpr.into(), + Ok(IBRD) =3D> self.ibrd.into(), + Ok(LCR_H) =3D> u16::from(self.line_control).into(), + Ok(CR) =3D> { + // We exercise our self-control. + u16::from(self.control).into() + } + Ok(FLS) =3D> self.ifl.into(), + Ok(IMSC) =3D> self.int_enabled.into(), + Ok(RIS) =3D> self.int_level.into(), + Ok(MIS) =3D> u64::from(self.int_level & self.int_enabled), + Ok(ICR) =3D> { + // "The UARTICR Register is the interrupt clear register a= nd is write-only" + // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, = UARTICR + 0 + } + Ok(DMACR) =3D> self.dmacr.into(), + } + } + + pub fn write(&mut self, offset: hwaddr, value: u64) { + // eprintln!("write offset {offset} value {value}"); + use RegisterOffset::*; + let value: u32 =3D value as u32; + match RegisterOffset::try_from(offset) { + Err(_bad_offset) =3D> { + eprintln!("write bad offset {offset} value {value}"); + } + Ok(DR) =3D> { + // ??? Check if transmitter is enabled. + let ch: u8 =3D value as u8; + // XXX this blocks entire thread. Rewrite to use + // qemu_chr_fe_write and background I/O callbacks + unsafe { + qemu_chr_fe_write_all(addr_of_mut!(self.char_backend),= &ch, 1); + } + self.loopback_tx(value); + self.int_level |=3D registers::INT_TX; + self.update(); + } + Ok(RSR) =3D> { + self.receive_status_error_clear =3D 0.into(); + } + Ok(FR) =3D> { + // flag writes are ignored + } + Ok(ILPR) =3D> { + self.ilpr =3D value; + } + Ok(IBRD) =3D> { + self.ibrd =3D value; + } + Ok(FBRD) =3D> { + self.fbrd =3D value; + } + Ok(LCR_H) =3D> { + let value =3D value as u16; + let new_val: registers::LineControl =3D value.into(); + // Reset the FIFO state on FIFO enable or disable + if bool::from(self.line_control.fifos_enabled()) + ^ bool::from(new_val.fifos_enabled()) + { + self.reset_fifo(); + } + if self.line_control.send_break() ^ new_val.send_break() { + let mut break_enable: c_int =3D new_val.send_break().i= nto(); + unsafe { + qemu_chr_fe_ioctl( + addr_of_mut!(self.char_backend), + CHR_IOCTL_SERIAL_SET_BREAK as i32, + addr_of_mut!(break_enable).cast::(), + ); + } + self.loopback_break(break_enable > 0); + } + self.line_control =3D new_val; + self.set_read_trigger(); + } + Ok(CR) =3D> { + // ??? Need to implement the enable bit. + let value =3D value as u16; + self.control =3D value.into(); + self.loopback_mdmctrl(); + } + Ok(FLS) =3D> { + self.ifl =3D value; + self.set_read_trigger(); + } + Ok(IMSC) =3D> { + self.int_enabled =3D value; + self.update(); + } + Ok(RIS) =3D> {} + Ok(MIS) =3D> {} + Ok(ICR) =3D> { + self.int_level &=3D !value; + self.update(); + } + Ok(DMACR) =3D> { + self.dmacr =3D value; + if value & 3 > 0 { + // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemente= d\n"); + eprintln!("pl011: DMA not implemented"); + } + } + } + } + + #[inline] + fn loopback_tx(&mut self, value: u32) { + if !self.loopback_enabled() { + return; + } + + // Caveat: + // + // In real hardware, TX loopback happens at the serial-bit level + // and then reassembled by the RX logics back into bytes and placed + // into the RX fifo. That is, loopback happens after TX fifo. + // + // Because the real hardware TX fifo is time-drained at the frame + // rate governed by the configured serial format, some loopback + // bytes in TX fifo may still be able to get into the RX fifo + // that could be full at times while being drained at software + // pace. + // + // In such scenario, the RX draining pace is the major factor + // deciding which loopback bytes get into the RX fifo, unless + // hardware flow-control is enabled. + // + // For simplicity, the above described is not emulated. + self.put_fifo(value); + } + + fn loopback_mdmctrl(&mut self) { + if !self.loopback_enabled() { + return; + } + + /* + * Loopback software-driven modem control outputs to modem status = inputs: + * FR.RI <=3D CR.Out2 + * FR.DCD <=3D CR.Out1 + * FR.CTS <=3D CR.RTS + * FR.DSR <=3D CR.DTR + * + * The loopback happens immediately even if this call is triggered + * by setting only CR.LBE. + * + * CTS/RTS updates due to enabled hardware flow controls are not + * dealt with here. + */ + + //fr =3D s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD | + // PL011_FLAG_DSR | PL011_FLAG_CTS); + //fr |=3D (cr & CR_OUT2) ? PL011_FLAG_RI : 0; + //fr |=3D (cr & CR_OUT1) ? PL011_FLAG_DCD : 0; + //fr |=3D (cr & CR_RTS) ? PL011_FLAG_CTS : 0; + //fr |=3D (cr & CR_DTR) ? PL011_FLAG_DSR : 0; + // + self.flags.set_ring_indicator(self.control.out_2()); + self.flags.set_data_carrier_detect(self.control.out_1()); + self.flags.set_clear_to_send(self.control.request_to_send()); + self.flags + .set_data_set_ready(self.control.data_transmit_ready()); + + // Change interrupts based on updated FR + let mut il =3D self.int_level; + + il &=3D !Interrupt::MS; + //il |=3D (fr & PL011_FLAG_DSR) ? INT_DSR : 0; + //il |=3D (fr & PL011_FLAG_DCD) ? INT_DCD : 0; + //il |=3D (fr & PL011_FLAG_CTS) ? INT_CTS : 0; + //il |=3D (fr & PL011_FLAG_RI) ? INT_RI : 0; + + if self.flags.data_set_ready() { + il |=3D Interrupt::DSR as u32; + } + if self.flags.data_carrier_detect() { + il |=3D Interrupt::DCD as u32; + } + if self.flags.clear_to_send() { + il |=3D Interrupt::CTS as u32; + } + if self.flags.ring_indicator() { + il |=3D Interrupt::RI as u32; + } + self.int_level =3D il; + self.update(); + } + + fn loopback_break(&mut self, enable: bool) { + if enable { + self.loopback_tx(DATA_BREAK); + } + } + + fn set_read_trigger(&mut self) { + //#if 0 + // /* The docs say the RX interrupt is triggered when the FIFO = exceeds + // the threshold. However linux only reads the FIFO in resp= onse to an + // interrupt. Triggering the interrupt when the FIFO is non= -empty seems + // to make things work. */ + // if (s->lcr & LCR_FEN) + // s->read_trigger =3D (s->ifl >> 1) & 0x1c; + // else + //#endif + self.read_trigger =3D 1; + } + + pub fn realize(&mut self) { + unsafe { + qemu_chr_fe_set_handlers( + addr_of_mut!(self.char_backend), + Some(pl011_can_receive), + Some(pl011_receive), + Some(pl011_event), + None, + addr_of_mut!(*self).cast::(), + core::ptr::null_mut(), + true, + ); + } + } + + pub fn reset(&mut self) { + self.line_control.reset(); + self.receive_status_error_clear.reset(); + self.dmacr =3D 0; + self.int_enabled =3D 0; + self.int_level =3D 0; + self.ilpr =3D 0; + self.ibrd =3D 0; + self.fbrd =3D 0; + self.read_trigger =3D 1; + self.ifl =3D 0x12; + self.control.reset(); + self.flags =3D 0.into(); + self.reset_fifo(); + } + + pub fn reset_fifo(&mut self) { + self.read_count =3D 0; + self.read_pos =3D 0; + + /* Reset FIFO flags */ + self.flags.reset(); + } + + pub fn can_receive(&self) -> bool { + // trace_pl011_can_receive(s->lcr, s->read_count, r); + self.read_count < self.fifo_depth() + } + + pub fn event(&mut self, event: QEMUChrEvent) { + if event =3D=3D bindings::QEMUChrEvent_CHR_EVENT_BREAK && !self.fi= fo_enabled() { + self.put_fifo(DATA_BREAK); + self.receive_status_error_clear.set_break_error(true); + } + } + + #[inline] + pub fn fifo_enabled(&self) -> bool { + matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO) + } + + #[inline] + pub fn loopback_enabled(&self) -> bool { + self.control.enable_loopback() + } + + #[inline] + pub fn fifo_depth(&self) -> usize { + // Note: FIFO depth is expected to be power-of-2 + if self.fifo_enabled() { + return PL011_FIFO_DEPTH; + } + 1 + } + + pub fn put_fifo(&mut self, value: c_uint) { + let depth =3D self.fifo_depth(); + assert!(depth > 0); + let slot =3D (self.read_pos + self.read_count) & (depth - 1); + self.read_fifo[slot] =3D value; + self.read_count +=3D 1; + // s->flags &=3D ~PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(false); + if self.read_count =3D=3D depth { + //s->flags |=3D PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(true); + } + + if self.read_count =3D=3D self.read_trigger { + self.int_level |=3D registers::INT_RX; + self.update(); + } + } + + pub fn update(&mut self) { + let flags =3D self.int_level & self.int_enabled; + for (irq, i) in self.interrupts.iter().zip(IRQMASK) { + unsafe { qemu_set_irq(*irq, i32::from(flags & i !=3D 0)) }; + } + } +} + +/// Which bits in the interrupt status matter for each outbound IRQ line ? +pub const IRQMASK: [u32; 6] =3D [ + /* combined IRQ */ + Interrupt::E + | Interrupt::MS + | Interrupt::RT as u32 + | Interrupt::TX as u32 + | Interrupt::RX as u32, + Interrupt::RX as u32, + Interrupt::TX as u32, + Interrupt::RT as u32, + Interrupt::MS, + Interrupt::E, +]; + +#[no_mangle] +pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int { + assert!(!opaque.is_null()); + let state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_ref().can_receive().into() +} + +#[no_mangle] +pub unsafe extern "C" fn pl011_receive( + opaque: *mut core::ffi::c_void, + buf: *const u8, + size: core::ffi::c_int, +) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + if state.as_ref().loopback_enabled() { + return; + } + if size > 0 { + assert!(!buf.is_null()); + state.as_mut().put_fifo(*buf.cast::()) + } +} + +#[no_mangle] +pub unsafe extern "C" fn pl011_event(opaque: *mut core::ffi::c_void, event= : QEMUChrEvent) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().event(event) +} + +#[no_mangle] +pub unsafe extern "C" fn rust_pl011_create( + addr: u64, + irq: qemu_irq, + chr: *mut Chardev, +) -> *mut DeviceState { + let dev: *mut DeviceState =3D unsafe { qdev_new(PL011_ARM_INFO.name) }; + assert!(!dev.is_null()); + let sysbus: *mut SysBusDevice =3D dev as *mut SysBusDevice; + + unsafe { + qdev_prop_set_chr(dev, bindings::TYPE_CHARDEV.as_ptr(), chr); + sysbus_realize_and_unref(sysbus, addr_of!(error_fatal) as *mut *mu= t Error); + sysbus_mmio_map(sysbus, 0, addr); + sysbus_connect_irq(sysbus, 0, irq); + } + dev +} diff --git a/rust/pl011/src/device_class.rs b/rust/pl011/src/device_class.rs new file mode 100644 index 0000000000..a886731107 --- /dev/null +++ b/rust/pl011/src/device_class.rs @@ -0,0 +1,48 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use core::ptr::NonNull; + +use qemu_api::bindings::*; + +use crate::{definitions::VMSTATE_PL011, device::PL011State}; + +qemu_api::declare_properties! { + PL011_PROPERTIES, + qemu_api::define_property!( + c"chardev", + PL011State, + char_backend, + unsafe { &qdev_prop_chr }, + CharBackend + ), + qemu_api::define_property!( + c"migrate-clk", + PL011State, + migrate_clock, + unsafe { &qdev_prop_bool }, + bool + ), +} + +qemu_api::device_class_init! { + pl011_class_init, + props =3D> PL011_PROPERTIES, + realize_fn =3D> Some(pl011_realize), + reset_fn =3D> Some(pl011_reset), + vmsd =3D> VMSTATE_PL011, +} + +#[no_mangle] +pub unsafe extern "C" fn pl011_realize(dev: *mut DeviceState, _errp: *mut = *mut Error) { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().realize(); +} + +#[no_mangle] +pub unsafe extern "C" fn pl011_reset(dev: *mut DeviceState) { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().reset(); +} diff --git a/rust/pl011/src/lib.rs b/rust/pl011/src/lib.rs new file mode 100644 index 0000000000..ec7ed04fc0 --- /dev/null +++ b/rust/pl011/src/lib.rs @@ -0,0 +1,556 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later +// +// PL011 QEMU Device Model +// +// This library implements a device model for the PrimeCell=C2=AE UART (PL= 011) +// device in QEMU. +// +#![doc =3D include_str!("../README.md")] +//! # Library crate +//! +//! See [`PL011State`](crate::device::PL011State) for the device model typ= e and +//! the [`registers`] module for register types. + +pub mod definitions; +pub mod device; +pub mod device_class; +pub mod memory_ops; + +/// Offset of each register from the base memory address of the device. +/// +/// # Source +/// ARM DDI 0183G, Table 3-1 p.3-3 +#[doc(alias =3D "offset")] +#[allow(non_camel_case_types)] +#[repr(u64)] +#[derive(Debug)] +pub enum RegisterOffset { + /// Data Register + /// + /// A write to this register initiates the actual data transmission + #[doc(alias =3D "UARTDR")] + DR =3D 0x000, + /// Receive Status Register or Error Clear Register + #[doc(alias =3D "UARTRSR")] + #[doc(alias =3D "UARTECR")] + RSR =3D 0x004, + /// Flag Register + /// + /// A read of this register shows if transmission is complete + #[doc(alias =3D "UARTFR")] + FR =3D 0x018, + /// Fractional Baud Rate Register + /// + /// responsible for baud rate speed + #[doc(alias =3D "UARTFBRD")] + FBRD =3D 0x028, + /// `IrDA` Low-Power Counter Register + #[doc(alias =3D "UARTILPR")] + ILPR =3D 0x020, + /// Integer Baud Rate Register + /// + /// Responsible for baud rate speed + #[doc(alias =3D "UARTIBRD")] + IBRD =3D 0x024, + /// line control register (data frame format) + #[doc(alias =3D "UARTLCR_H")] + LCR_H =3D 0x02C, + /// Toggle UART, transmission or reception + #[doc(alias =3D "UARTCR")] + CR =3D 0x030, + /// Interrupt FIFO Level Select Register + #[doc(alias =3D "UARTIFLS")] + FLS =3D 0x034, + /// Interrupt Mask Set/Clear Register + #[doc(alias =3D "UARTIMSC")] + IMSC =3D 0x038, + /// Raw Interrupt Status Register + #[doc(alias =3D "UARTRIS")] + RIS =3D 0x03C, + /// Masked Interrupt Status Register + #[doc(alias =3D "UARTMIS")] + MIS =3D 0x040, + /// Interrupt Clear Register + #[doc(alias =3D "UARTICR")] + ICR =3D 0x044, + /// DMA control Register + #[doc(alias =3D "UARTDMACR")] + DMACR =3D 0x048, + ///// Reserved, offsets `0x04C` to `0x07C`. + //Reserved =3D 0x04C, +} + +impl core::convert::TryFrom for RegisterOffset { + type Error =3D u64; + + fn try_from(value: u64) -> Result { + macro_rules! case { + ($($discriminant:ident),*$(,)*) =3D> { + /* check that matching on all macro arguments compiles, wh= ich means we are not + * missing any enum value; if the type definition ever cha= nges this will stop + * compiling. + */ + const fn _assert_exhaustive(val: RegisterOffset) { + match val { + $(RegisterOffset::$discriminant =3D> (),)* + } + } + + match value { + $(x if x =3D=3D Self::$discriminant as u64 =3D> Ok(Sel= f::$discriminant),)* + _ =3D> Err(value), + } + } + } + case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, = MIS, ICR, DMACR } + } +} + +pub mod registers { + //! Device registers exposed as typed structs which are backed by arbi= trary + //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. + //! + //! All PL011 registers are essentially 32-bit wide, but are typed her= e as + //! bitmaps with only the necessary width. That is, if a struct bitmap + //! in this module is for example 16 bits long, it should be conceived + //! as a 32-bit register where the unmentioned higher bits are always + //! unused thus treated as zero when read or written. + use bilge::prelude::*; + + // TODO: FIFO Mode has different semantics + /// Data Register, `UARTDR` + /// + /// The `UARTDR` register is the data register. + /// + /// For words to be transmitted: + /// + /// - if the FIFOs are enabled, data written to this location is pushe= d onto + /// the transmit + /// FIFO + /// - if the FIFOs are not enabled, data is stored in the transmitter + /// holding register (the + /// bottom word of the transmit FIFO). + /// + /// The write operation initiates transmission from the UART. The data= is + /// prefixed with a start bit, appended with the appropriate parity bit + /// (if parity is enabled), and a stop bit. The resultant word is then + /// transmitted. + /// + /// For received words: + /// + /// - if the FIFOs are enabled, the data byte and the 4-bit status (br= eak, + /// frame, parity, + /// and overrun) is pushed onto the 12-bit wide receive FIFO + /// - if the FIFOs are not enabled, the data byte and status are store= d in + /// the receiving + /// holding register (the bottom word of the receive FIFO). + /// + /// The received data byte is read by performing reads from the `UARTD= R` + /// register along with the corresponding status information. The stat= us + /// information can also be read by a read of the `UARTRSR/UARTECR` + /// register. + /// + /// # Note + /// + /// You must disable the UART before any of the control registers are + /// reprogrammed. When the UART is disabled in the middle of + /// transmission or reception, it completes the current character befo= re + /// stopping. + /// + /// # Source + /// ARM DDI 0183G 3.3.1 Data Register, UARTDR + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + #[doc(alias =3D "UARTDR")] + pub struct Data { + _reserved: u4, + pub data: u8, + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + } + + // TODO: FIFO Mode has different semantics + /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` + /// + /// The UARTRSR/UARTECR register is the receive status register/error = clear + /// register. Receive status can also be read from the `UARTRSR` + /// register. If the status is read from this register, then the status + /// information for break, framing and parity corresponds to the + /// data character read from the [Data register](Data), `UARTDR` prior= to + /// reading the UARTRSR register. The status information for overrun is + /// set immediately when an overrun condition occurs. + /// + /// + /// # Note + /// The received data character must be read first from the [Data + /// Register](Data), `UARTDR` before reading the error status associat= ed + /// with that data character from the `UARTRSR` register. This read + /// sequence cannot be reversed, because the `UARTRSR` register is + /// updated only when a read occurs from the `UARTDR` register. Howeve= r, + /// the status information can also be obtained by reading the `UARTDR` + /// register + /// + /// # Source + /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, + /// UARTRSR/UARTECR + #[bitsize(8)] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct ReceiveStatusErrorClear { + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + _reserved_unpredictable: u4, + } + + impl ReceiveStatusErrorClear { + pub fn reset(&mut self) { + // All the bits are cleared to 0 on reset. + *self =3D 0.into(); + } + } + + impl Default for ReceiveStatusErrorClear { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Flag Register, `UARTFR` + #[doc(alias =3D "UARTFR")] + pub struct Flags { + /// CTS Clear to send. This bit is the complement of the UART clea= r to + /// send, `nUARTCTS`, modem status input. That is, the bit is 1 + /// when `nUARTCTS` is LOW. + pub clear_to_send: bool, + /// DSR Data set ready. This bit is the complement of the UART dat= a set + /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 w= hen + /// `nUARTDSR` is LOW. + pub data_set_ready: bool, + /// DCD Data carrier detect. This bit is the complement of the UAR= T data + /// carrier detect, `nUARTDCD`, modem status input. That is, the b= it is + /// 1 when `nUARTDCD` is LOW. + pub data_carrier_detect: bool, + /// BUSY UART busy. If this bit is set to 1, the UART is busy + /// transmitting data. This bit remains set until the complete + /// byte, including all the stop bits, has been sent from the + /// shift register. This bit is set as soon as the transmit FIFO + /// becomes non-empty, regardless of whether the UART is enabled + /// or not. + pub busy: bool, + /// RXFE Receive FIFO empty. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the receive holding + /// register is empty. If the FIFO is enabled, the RXFE bit is + /// set when the receive FIFO is empty. + pub receive_fifo_empty: bool, + /// TXFF Transmit FIFO full. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the transmit holding + /// register is full. If the FIFO is enabled, the TXFF bit is + /// set when the transmit FIFO is full. + pub transmit_fifo_full: bool, + /// RXFF Receive FIFO full. The meaning of this bit depends on the= state + /// of the FEN bit in the UARTLCR_H register. If the FIFO is + /// disabled, this bit is set when the receive holding register + /// is full. If the FIFO is enabled, the RXFF bit is set when + /// the receive FIFO is full. + pub receive_fifo_full: bool, + /// Transmit FIFO empty. The meaning of this bit depends on the st= ate of + /// the FEN bit in the [Line Control register](LineControl), + /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the + /// transmit holding register is empty. If the FIFO is enabled, + /// the TXFE bit is set when the transmit FIFO is empty. This + /// bit does not indicate if there is data in the transmit shift + /// register. + pub transmit_fifo_empty: bool, + /// `RI`, is `true` when `nUARTRI` is `LOW`. + pub ring_indicator: bool, + _reserved_zero_no_modify: u7, + } + + impl Flags { + pub fn reset(&mut self) { + // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE a= re 1 + self.set_receive_fifo_full(false); + self.set_transmit_fifo_full(false); + self.set_busy(false); + self.set_receive_fifo_empty(true); + self.set_transmit_fifo_empty(true); + } + } + + impl Default for Flags { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Line Control Register, `UARTLCR_H` + #[doc(alias =3D "UARTLCR_H")] + pub struct LineControl { + /// 15:8 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u8, + /// 7 SPS Stick parity select. + /// 0 =3D stick parity is disabled + /// 1 =3D either: + /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt= ed and checked + /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is + /// transmitted and checked as a 0. This bit has no effect when + /// the PEN bit disables parity checking and generation. See Table= 3-11 + /// on page 3-14 for the parity truth table. + pub sticky_parity: bool, + /// WLEN Word length. These bits indicate the number of data bits + /// transmitted or received in a frame as follows: b11 =3D 8 bits + /// b10 =3D 7 bits + /// b01 =3D 6 bits + /// b00 =3D 5 bits. + pub word_length: WordLength, + /// FEN Enable FIFOs: + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO + /// buffers are enabled (FIFO mode). + pub fifos_enabled: Mode, + /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop= bits + /// are transmitted at the end of the frame. The receive + /// logic does not check for two stop bits being received. + pub two_stops_bits: bool, + /// EPS Even parity select. Controls the type of parity the UART u= ses + /// during transmission and reception: + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + /// This bit has no effect when the `PEN` bit disables parity chec= king + /// and generation. See Table 3-11 on page 3-14 for the parity + /// truth table. + pub parity: Parity, + /// 1 PEN Parity enable: + /// + /// - 0 =3D parity is disabled and no parity bit added to the data= frame + /// - 1 =3D parity checking and generation is enabled. + /// + /// See Table 3-11 on page 3-14 for the parity truth table. + pub parity_enabled: bool, + /// BRK Send break. + /// + /// If this bit is set to `1`, a low-level is continually output o= n the + /// `UARTTXD` output, after completing transmission of the + /// current character. For the proper execution of the break comma= nd, + /// the software must set this bit for at least two complete + /// frames. For normal use, this bit must be cleared to `0`. + pub send_break: bool, + } + + impl LineControl { + pub fn reset(&mut self) { + // All the bits are cleared to 0 when reset. + *self =3D 0.into(); + } + } + + impl Default for LineControl { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `EPS` "Even parity select", field of [Line Control + /// register](LineControl). + pub enum Parity { + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + Odd =3D 0, + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + Even =3D 1, + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control + /// register](LineControl). + pub enum Mode { + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers + Character =3D 0, + /// 1 =3D transmit and receive FIFO buffers are enabled (FIFO mode= ). + FIFO =3D 1, + } + + impl From for bool { + fn from(val: Mode) -> Self { + matches!(val, Mode::FIFO) + } + } + + #[bitsize(2)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `WLEN` Word length, field of [Line Control register](LineControl). + /// + /// These bits indicate the number of data bits transmitted or receive= d in a + /// frame as follows: + pub enum WordLength { + /// b11 =3D 8 bits + _8Bits =3D 0b11, + /// b10 =3D 7 bits + _7Bits =3D 0b10, + /// b01 =3D 6 bits + _6Bits =3D 0b01, + /// b00 =3D 5 bits. + _5Bits =3D 0b00, + } + + /// Control Register, `UARTCR` + /// + /// The `UARTCR` register is the control register. All the bits are cl= eared + /// to `0` on reset except for bits `9` and `8` that are set to `1`. + /// + /// # Source + /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 + #[bitsize(16)] + #[doc(alias =3D "UARTCR")] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct Control { + /// `UARTEN` UART enable: 0 =3D UART is disabled. If the UART is d= isabled + /// in the middle of transmission or reception, it completes the c= urrent + /// character before stopping. 1 =3D the UART is enabled. Data + /// transmission and reception occurs for either UART signals or S= IR + /// signals depending on the setting of the SIREN bit. + pub enable_uart: bool, + /// `SIREN` `SIR` enable: 0 =3D IrDA SIR ENDEC is disabled. `nSIRO= UT` + /// remains LOW (no light pulse generated), and signal transitions= on + /// SIRIN have no effect. 1 =3D IrDA SIR ENDEC is enabled. Data is + /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains= HIGH, + /// in the marking state. Signal transitions on UARTRXD or modem s= tatus + /// inputs have no effect. This bit has no effect if the UARTEN bit + /// disables the UART. + pub enable_sir: bool, + /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA enc= oding + /// mode. If this bit is cleared to 0, low-level bits are transmit= ted as + /// an active high pulse with a width of 3/ 16th of the bit period= . If + /// this bit is set to 1, low-level bits are transmitted with a pu= lse + /// width that is 3 times the period of the IrLPBaud16 input signa= l, + /// regardless of the selected bit rate. Setting this bit uses less + /// power, but might reduce transmission distances. + pub sir_lowpower_irda_mode: u1, + /// Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u4, + /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN b= it is + /// set to 1 and the SIRTEST bit in the Test Control register, UAR= TTCR + /// on page 4-5 is set to 1, then the nSIROUT path is inverted, an= d fed + /// through to the SIRIN path. The SIRTEST bit in the test registe= r must + /// be set to 1 to override the normal half-duplex SIR operation. = This + /// must be the requirement for accessing the test registers during + /// normal operation, and SIRTEST must be cleared to 0 when loopba= ck + /// testing is finished. This feature reduces the amount of extern= al + /// coupling required during system test. If this bit is set to 1,= and + /// the SIRTEST bit is set to 0, the UARTTXD path is fed through t= o the + /// UARTRXD path. In either SIR mode or UART mode, when this bit i= s set, + /// the modem outputs are also fed through to the modem inputs. Th= is bit + /// is cleared to 0 on reset, to disable loopback. + pub enable_loopback: bool, + /// `TXE` Transmit enable. If this bit is set to 1, the transmit s= ection + /// of the UART is enabled. Data transmission occurs for either UA= RT + /// signals, or SIR signals depending on the setting of the SIREN = bit. + /// When the UART is disabled in the middle of transmission, it + /// completes the current character before stopping. + pub enable_transmit: bool, + /// `RXE` Receive enable. If this bit is set to 1, the receive sec= tion + /// of the UART is enabled. Data reception occurs for either UART + /// signals or SIR signals depending on the setting of the SIREN b= it. + /// When the UART is disabled in the middle of reception, it compl= etes + /// the current character before stopping. + pub enable_receive: bool, + /// `DTR` Data transmit ready. This bit is the complement of the U= ART + /// data transmit ready, `nUARTDTR`, modem status output. That is,= when + /// the bit is programmed to a 1 then `nUARTDTR` is LOW. + pub data_transmit_ready: bool, + /// `RTS` Request to send. This bit is the complement of the UART + /// request to send, `nUARTRTS`, modem status output. That is, whe= n the + /// bit is programmed to a 1 then `nUARTRTS` is LOW. + pub request_to_send: bool, + /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1= `) + /// modem status output. That is, when the bit is programmed to a = 1 the + /// output is 0. For DTE this can be used as Data Carrier Detect (= DCD). + pub out_1: bool, + /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2= `) + /// modem status output. That is, when the bit is programmed to a = 1, the + /// output is 0. For DTE this can be used as Ring Indicator (RI). + pub out_2: bool, + /// `RTSEn` RTS hardware flow control enable. If this bit is set t= o 1, + /// RTS hardware flow control is enabled. Data is only requested w= hen + /// there is space in the receive FIFO for it to be received. + pub rts_hardware_flow_control_enable: bool, + /// `CTSEn` CTS hardware flow control enable. If this bit is set t= o 1, + /// CTS hardware flow control is enabled. Data is only transmitted= when + /// the `nUARTCTS` signal is asserted. + pub cts_hardware_flow_control_enable: bool, + } + + impl Control { + pub fn reset(&mut self) { + *self =3D 0.into(); + self.set_enable_receive(true); + self.set_enable_transmit(true); + } + } + + impl Default for Control { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC + pub const INT_OE: u32 =3D 1 << 10; + pub const INT_BE: u32 =3D 1 << 9; + pub const INT_PE: u32 =3D 1 << 8; + pub const INT_FE: u32 =3D 1 << 7; + pub const INT_RT: u32 =3D 1 << 6; + pub const INT_TX: u32 =3D 1 << 5; + pub const INT_RX: u32 =3D 1 << 4; + pub const INT_DSR: u32 =3D 1 << 3; + pub const INT_DCD: u32 =3D 1 << 2; + pub const INT_CTS: u32 =3D 1 << 1; + pub const INT_RI: u32 =3D 1 << 0; + pub const INT_E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const INT_MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + + #[repr(u32)] + pub enum Interrupt { + OE =3D 1 << 10, + BE =3D 1 << 9, + PE =3D 1 << 8, + FE =3D 1 << 7, + RT =3D 1 << 6, + TX =3D 1 << 5, + RX =3D 1 << 4, + DSR =3D 1 << 3, + DCD =3D 1 << 2, + CTS =3D 1 << 1, + RI =3D 1 << 0, + } + + impl Interrupt { + pub const E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + } +} + +// TODO: You must disable the UART before any of the control registers are +// reprogrammed. When the UART is disabled in the middle of transmission or +// reception, it completes the current character before stopping diff --git a/rust/pl011/src/memory_ops.rs b/rust/pl011/src/memory_ops.rs new file mode 100644 index 0000000000..6144d28586 --- /dev/null +++ b/rust/pl011/src/memory_ops.rs @@ -0,0 +1,45 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use core::{mem::MaybeUninit, ptr::NonNull}; + +use qemu_api::bindings::*; + +use crate::device::PL011State; + +pub static PL011_OPS: MemoryRegionOps =3D MemoryRegionOps { + read: Some(pl011_read), + write: Some(pl011_write), + read_with_attrs: None, + write_with_attrs: None, + endianness: device_endian_DEVICE_NATIVE_ENDIAN, + valid: unsafe { MaybeUninit::::zeroed()= .assume_init() }, + impl_: MemoryRegionOps__bindgen_ty_2 { + min_access_size: 4, + max_access_size: 4, + ..unsafe { MaybeUninit::::zeroed().= assume_init() } + }, +}; + +#[no_mangle] +unsafe extern "C" fn pl011_read( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + size: core::ffi::c_uint, +) -> u64 { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().read(addr, size) +} + +#[no_mangle] +unsafe extern "C" fn pl011_write( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + data: u64, + _size: core::ffi::c_uint, +) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().write(addr, data) +} --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89 From nobody Sun Nov 24 20:49:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1720095440; cv=none; d=zohomail.com; s=zohoarc; b=lQpMnJR1Fw4njwjrfJQY4VftLkS9b8LKgjHW7PZ8mPCbTQGCnFNDaKNwKPPj0Gg95RO2TEK7D5KZ/zQvVlIhipiPa7Jd3fQ2ns6zNyYq368ziHs0tFSxVBkKObLy+lxpco8s6Q6lXK3FiG+R9Fm4zMsQm/ggayPj3rn7hDKy57U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720095440; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xt+VxmwzqqK9gMrTvz+AxGQbrZZuHkdN6tBaDv95dAw=; b=LnKD5/wvUMiLkLM2jNsoHOYf8wx8mcmXBlA1tFV1zGxrkjsHNnU3VFxkPEy0Y/AmwQfdgkkW9qauxs9sVrRfnbmIcxxLdDc7FA4OKqx0V7bUE8fquWXb7bEJdc5nyTO9IhPDI176d+rWfzjMjg1Rj5Fpk8uBHz9ljI3CO6kb5Ts= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720095440974486.37242145713094; Thu, 4 Jul 2024 05:17:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPLOE-0007vV-Pe; Thu, 04 Jul 2024 08:16:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPLNn-0007ra-2s for qemu-devel@nongnu.org; Thu, 04 Jul 2024 08:16:20 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sPLNi-0002Ri-Iy for qemu-devel@nongnu.org; Thu, 04 Jul 2024 08:16:14 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-42573d3f7e4so3763985e9.0 for ; Thu, 04 Jul 2024 05:16:09 -0700 (PDT) Received: from localhost.localdomain (adsl-241.37.6.160.tellas.gr. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720095442603100008 Content-Type: text/plain; charset="utf-8" Set rust source code to diff=3Drust (built-in with new git versions) and merge=3Dbinary for Cargo.lock files (they should not be merged but auto-generated by cargo) Signed-off-by: Manos Pitsidianakis Reviewed-by: Alex Benn=C3=A9e --- .gitattributes | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitattributes b/.gitattributes index a217cb7bfe..6dc6383d3d 100644 --- a/.gitattributes +++ b/.gitattributes @@ -2,3 +2,6 @@ *.h.inc diff=3Dc *.m diff=3Dobjc *.py diff=3Dpython +*.rs diff=3Drust +*.rs.inc diff=3Drust +Cargo.lock diff=3Dtoml merge=3Dbinary --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89 From nobody Sun Nov 24 20:49:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[37.6.160.241]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a2ca5casm22471015e9.32.2024.07.04.05.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 05:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720095369; x=1720700169; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H+7NsildlwdPQvya89L8R2V+Gz+X4TQT3UR+alA0+QE=; b=mZBjo+c09hxXAhZkEXBUDNp5knnbh8yEgHdn5jGmztCw7MqbIJ/+7oISi4ZGnUAx9x l+mHd9eT0LLg6Ufy+tAmtsvNSm9tAIym37wPNa2evWF+e4sqJTeo2G2wCVfzKLJtXksi LkIPAHeI+h8dQocaXiwoxAPwj8WPV4Z9RBmKD4zmgZBrmgPi+Va9jo1xL/neSkfxdCBt XwE85e5x64laAwh3nDKUL3NbXbbwK6ObV1SHD3IuObH6MkwvWW1H7OP9/Wl9DRt4p2Xp NDfrV9c22qurGTZNUReEZh/PUtZKYgIhVcDM8BdC3dv5WdEwqYsfs02Wt872xYVzy1bQ 2KDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720095369; x=1720700169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H+7NsildlwdPQvya89L8R2V+Gz+X4TQT3UR+alA0+QE=; b=bch5AJBcXMsXBk+h3M0usijiX/xtn5YshvbFsgBAhSkLiKWth12M9vi9At9K6D0bK3 J2zVyGU8QhdE9PcVoNls17upnNm1xhgoaYWQLczv6CMzlgHhnzTHqzOKZhb2MFYQYebZ y6ZoA6rLOgTs5s0AiKDprK1J7RkpzcMGvaAd9J1mbgROQVFf7nBB0L2FoifxgSmD1dbq ZI+M1OBwfc3DqvstXyqVZHC6AdlwW9z+KqRypywXIoMfNqsORNZN/1KMf+P59AhySeSg ugzNKRdpIrBgsyI6otV86rnUSC4n+Ivf4mBaqoWXjZahHKJd/fxMdbXGO6IVX604eHjO oQaQ== X-Gm-Message-State: AOJu0YyCMqiPhIov++VERC75t3KTQADIpmfnUNmILYsE0f9FEIC1Yrua weGFuSWiYhGtzU4ekxFXBDZICWec9u0nXkYtjDDVp+/GFL3AvhsrEXf0b9asFM2n4yG6NXRfHbe 1pYs= X-Google-Smtp-Source: AGHT+IGywjsHMPfl5vR3+VrjMeCv32eUtm9GB5lycr+SGGsxF6qtGyeWiyAbXxg006XO55Zo5i31Tg== X-Received: by 2002:a2e:be0f:0:b0:2ec:5699:5e6 with SMTP id 38308e7fff4ca-2ee8ed9fc91mr12525301fa.26.1720095369553; Thu, 04 Jul 2024 05:16:09 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson , Wainer dos Santos Moschetta , Beraldo Leal Subject: [RFC PATCH v4 6/7] DO NOT MERGE: add rustdoc build for gitlab pages Date: Thu, 4 Jul 2024 15:15:42 +0300 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720095456419100010 Content-Type: text/plain; charset="utf-8" Deploy the generated rustdocs for my personal rust qemu fork on gitlab. The URL is: https://rust-for-qemu-epilys-aebb06ca9f9adfe6584811c14ae44156501d935ba4.git= lab.io/pl011/index.html Signed-off-by: Manos Pitsidianakis --- .gitlab-ci.d/buildtest.yml | 64 +++++++++++++++++++++++++++----------- 1 file changed, 45 insertions(+), 19 deletions(-) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 0eec570310..a2fedc87bd 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -716,31 +716,57 @@ build-tools-and-docs-debian: # For contributor forks we want to publish from any repo so # that users can see the results of their commits, regardless # of what topic branch they're currently using +# pages: +# extends: .base_job_template +# image: $CI_REGISTRY_IMAGE/qemu/debian:$QEMU_CI_CONTAINER_TAG +# stage: test +# needs: +# - job: build-tools-and-docs-debian +# script: +# - mkdir -p public +# # HTML-ised source tree +# - make gtags +# # We unset variables to work around a bug in some htags versions +# # which causes it to fail when the environment is large +# - CI_COMMIT_MESSAGE=3D CI_COMMIT_TAG_MESSAGE=3D htags +# -anT --tree-view=3Dfiletree -m qemu_init +# -t "Welcome to the QEMU sourcecode" +# - mv HTML public/src +# # Project documentation +# - make -C build install DESTDIR=3D$(pwd)/temp-install +# - mv temp-install/usr/local/share/doc/qemu/* public/ +# artifacts: +# when: on_success +# paths: +# - public +# variables: +# QEMU_JOB_PUBLISH: 1 +# The Docker image that will be used to build your app pages: - extends: .base_job_template - image: $CI_REGISTRY_IMAGE/qemu/debian:$QEMU_CI_CONTAINER_TAG - stage: test - needs: - - job: build-tools-and-docs-debian + image: rust:latest script: - - mkdir -p public - # HTML-ised source tree - - make gtags - # We unset variables to work around a bug in some htags versions - # which causes it to fail when the environment is large - - CI_COMMIT_MESSAGE=3D CI_COMMIT_TAG_MESSAGE=3D htags - -anT --tree-view=3Dfiletree -m qemu_init - -t "Welcome to the QEMU sourcecode" - - mv HTML public/src - # Project documentation - - make -C build install DESTDIR=3D$(pwd)/temp-install - - mv temp-install/usr/local/share/doc/qemu/* public/ + - rustup component add rustfmt + - DEBIAN_FRONTEND=3Dnoninteractive apt-get update -y + - DEBIAN_FRONTEND=3Dnoninteractive apt-get install -y python3-venv mes= on libgcrypt20-dev zlib1g-dev autoconf automake libtool bison flex git libg= lib2.0-dev libfdt-dev libpixman-1-dev ninja-build make libclang-14-dev + - cargo install bindgen-cli + - mkdir ./build/ + - cd ./build/ + - ../configure --enable-system --disable-kvm --target-list=3Daarch64-s= oftmmu --enable-with-rust + - ninja "bindings-aarch64-softmmu.rs" + - cp ./bindings-aarch64-softmmu.rs ../rust/qemu-api/src/bindings.rs.inc + - cd ../rust/pl011/ + - cargo tree --depth 1 -e normal --prefix none | cut -d' ' -f1 | xargs + printf -- '-p %s\n' | xargs cargo doc --no-deps --document-private-= items --target x86_64-unknown-linux-gnu + - cd ./../.. + - mv ./rust/pl011/target/x86_64-unknown-linux-gnu/doc ./public artifacts: when: on_success paths: - public - variables: - QEMU_JOB_PUBLISH: 1 + rules: + # This ensures that only pushes to the default branch will trigger + # a pages deploy + - if: $CI_COMMIT_REF_NAME =3D=3D $CI_DEFAULT_BRANCH =20 coverity: image: $CI_REGISTRY_IMAGE/qemu/fedora:$QEMU_CI_CONTAINER_TAG --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89 From nobody Sun Nov 24 20:49:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[37.6.160.241]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a2ca5casm22471015e9.32.2024.07.04.05.16.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 05:16:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720095372; x=1720700172; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sebo8kp7DAxDc5R9inOIScJcgh+uRNdHOYeHTAuds3E=; b=PiWzHlbnjoxKZgAhW/047cEQbBQSLywuXkRu5SdeXtysfq1P2pKUwblzvuuuuXh7FE HxVqVLFwY/+XYERhebaL3e9sQzXrc+qdkibv8+XplWnGe8X6vDRUwStBBgevveBRC0QR Dgu4vGFl+TRXZrfwpboIW1T632DgiTaJCjUhvBrGBik6nBGnp9jSsXNZqlggCux+9HDq 3kQwxHtApOPGQCIyyTzcgg4vnSO62rLclRwewHbn5xmqwMkKyP8Pwka/BErFlvZ1Zy8f VyuGbwo93sSYATm0E2T9QoP2C97PUxwFQ7HwyafaB43V1HChuruFgZIblYpVrBsXWQVs +U4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720095372; x=1720700172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sebo8kp7DAxDc5R9inOIScJcgh+uRNdHOYeHTAuds3E=; b=w8zcoTaxAp6NOkIBVIev/gpPOyIKm4GQYdDuMYpK4maT2I3EqNuxZYw3qANgbxfl0k AV4N5nb9QpPOZwlysjWKLU5gg3NTPx58WE9H7Mtg5prXJN67MnCN4z6IAzCAmiluMYDi PZQ/Gb4+oQGLlnf/a2mBu5d+vf+2Q9WRmOVhmzzZ/I0368Rn/0DqU4+rodCH7o7SuMml o6KGrkFDhlkPj2pJRqjnMh0K0n2kKKoyYH088QnAgVu8ctTcOMa63cfgd1FeESnIePKj k/bo2QJoFFn3wbIUkv+hKg1iypV56ZpoaUBd0lybqX8+q4Vz0t7Qm244Ajql/C7FMhbu kMcA== X-Gm-Message-State: AOJu0YxTgJhcl3jq2UKVloLQHVHglo/sj7qaZ4cZpfrHT7Mvs0SdTSY8 hc2y4FZcEQUA1GAmoBHnAsQC31HmkgrEcAReGf4Dc6qQPpaZf9TNOn8WRaUfqxN8k0dRBw97Jso KFjg= X-Google-Smtp-Source: AGHT+IGWtIyHVdRRDQf6UCO/aG+PUwZ52bIwCYcWjqtTvhy4DkR8vJ0g+c0CIxrJtgmEO3DIoK5/HA== X-Received: by 2002:a05:600c:158b:b0:422:62db:5a02 with SMTP id 5b1f17b1804b1-4264a4561d7mr10600945e9.32.1720095372023; Thu, 04 Jul 2024 05:16:12 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson , qemu-arm@nongnu.org Subject: [RFC PATCH v4 7/7] DO NOT MERGE: replace TYPE_PL011 with x-pl011-rust in arm virt machine Date: Thu, 4 Jul 2024 15:15:43 +0300 Message-ID: <99604de6015556c4dc57bef0fa89e53b1c42b4c6.1720094395.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720095454381100004 Content-Type: text/plain; charset="utf-8" Convenience patch for testing the rust device. Signed-off-by: Manos Pitsidianakis --- hw/arm/virt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b0c68d66a3..49dd0b815e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -929,7 +929,11 @@ static void create_uart(const VirtMachineState *vms, i= nt uart, int irq =3D vms->irqmap[uart]; const char compat[] =3D "arm,pl011\0arm,primecell"; const char clocknames[] =3D "uartclk\0apb_pclk"; +#ifdef CONFIG_WITH_RUST + DeviceState *dev =3D qdev_new("x-pl011-rust"); +#else DeviceState *dev =3D qdev_new(TYPE_PL011); +#endif SysBusDevice *s =3D SYS_BUS_DEVICE(dev); MachineState *ms =3D MACHINE(vms); =20 --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89