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Sat, 07 Mar 2026 23:18:53 -0800 (PST) From: Chao Liu To: Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier Cc: tangtao1634@phytium.com.cn, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 04/28] target/riscv: route in-debug exceptions back to the DM ROM Date: Sun, 8 Mar 2026 15:17:07 +0800 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1243; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dl1-x1243.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772954399231154100 Content-Type: text/plain; charset="utf-8" When a hart is already executing from the Debug Module ROM, redirect synchronous exceptions to the ROM exception entry instead of taking the normal trap path. This keeps the hart inside the Debug Module state machine and lets the ROM report command faults through its mailbox protocol. Signed-off-by: Chao Liu --- target/riscv/cpu_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e477016d4a..81b74f7e4a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -142,6 +142,9 @@ static bool riscv_sdext_enabled(CPURISCVState *env) return riscv_cpu_cfg(env)->ext_sdext; } =20 +/* DM ROM entry window offsets: exception vector is entry + 0x10 (0x810). = */ +#define RISCV_DEBUG_ROM_EXCEPTION_OFS 0x10 + /* * Debug Spec v1.0 Table 9: * - ebreak: dpc =3D address of the ebreak instruction. @@ -2326,6 +2329,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) return; } =20 + if (env->debug_mode && env->dm_rom_present) { + /* + * Exceptions taken while already in Debug Mode are handled by the + * DM ROM exception entry (0x810 in the backing ROM). + */ + env->pc =3D env->dm_halt_addr + RISCV_DEBUG_ROM_EXCEPTION_OFS; + return; + } + if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { --=20 2.53.0