From nobody Fri Nov 7 04:14:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546398305528662.4579408763931; Tue, 1 Jan 2019 19:05:05 -0800 (PST) Received: from localhost ([127.0.0.1]:41492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1geWq8-0005Ow-4o for importer@patchew.org; Tue, 01 Jan 2019 22:05:04 -0500 Received: from eggs.gnu.org ([208.118.235.92]:36604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1geWig-00073U-4f for qemu-devel@nongnu.org; Tue, 01 Jan 2019 21:57:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1geWic-0006zf-1I for qemu-devel@nongnu.org; Tue, 01 Jan 2019 21:57:22 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:48636) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1geWib-0006z6-Mt; Tue, 01 Jan 2019 21:57:17 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A14877456B9; Wed, 2 Jan 2019 03:57:16 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 78B7874569F; Wed, 2 Jan 2019 03:57:16 +0100 (CET) Message-Id: In-Reply-To: References: From: BALATON Zoltan Date: Wed, 02 Jan 2019 03:06:38 +0100 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH 1/8] smbus: Add a helper to generate SPD EEPROM data X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Paolo Bonzini , Aleksandar Markovic , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are several boards with SPD EEPROMs that are now using duplicated or slightly different hard coded data. Add a helper to generate SPD data for a memory module of given type and size that could be used by these boards (either as is or with further changes if needed) which should help cleaning this up and avoid further duplication. Signed-off-by: BALATON Zoltan --- hw/i2c/smbus_eeprom.c | 128 +++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/i2c/smbus.h | 3 ++ 2 files changed, 131 insertions(+) diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c index f18aa3de35..a1f51eb921 100644 --- a/hw/i2c/smbus_eeprom.c +++ b/hw/i2c/smbus_eeprom.c @@ -23,6 +23,8 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qemu/units.h" #include "hw/hw.h" #include "hw/i2c/i2c.h" #include "hw/i2c/smbus.h" @@ -162,3 +164,129 @@ void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256)); } } + +/* Generate SDRAM SPD EEPROM data describing a module of type and size */ +uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size) +{ + uint8_t *spd; + uint8_t nbanks; + uint16_t density; + uint32_t size; + int min_log2, max_log2, sz_log2; + int i; + + switch (type) { + case SDR: + min_log2 =3D 2; + max_log2 =3D 9; + break; + case DDR: + min_log2 =3D 5; + max_log2 =3D 12; + break; + case DDR2: + min_log2 =3D 7; + max_log2 =3D 14; + break; + default: + error_report("Unknown SDRAM type"); + abort(); + } + size =3D ram_size >> 20; /* work in terms of megabytes */ + if (size < 4) { + error_report("SDRAM size is too small"); + return NULL; + } + sz_log2 =3D 31 - clz32(size); + size =3D 1U << sz_log2; + if (ram_size > size * MiB) { + warn_report("SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, " + "truncating to %u MB", ram_size, size); + } + if (sz_log2 < min_log2) { + warn_report("Memory size is too small for SDRAM type, adjusting ty= pe"); + if (size >=3D 32) { + type =3D DDR; + min_log2 =3D 5; + max_log2 =3D 12; + } else { + type =3D SDR; + min_log2 =3D 2; + max_log2 =3D 9; + } + } + + nbanks =3D 1; + while (sz_log2 > max_log2 && nbanks < 8) { + sz_log2--; + nbanks++; + } + + if (size > (1ULL << sz_log2) * nbanks) { + warn_report("Memory size is too big for SDRAM, truncating"); + } + + /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware = */ + if (nbanks =3D=3D 1 && sz_log2 > min_log2) { + sz_log2--; + nbanks++; + } + + density =3D 1ULL << (sz_log2 - 2); + switch (type) { + case DDR2: + density =3D (density & 0xe0) | (density >> 8 & 0x1f); + break; + case DDR: + density =3D (density & 0xf8) | (density >> 8 & 0x07); + break; + case SDR: + default: + density &=3D 0xff; + break; + } + + spd =3D g_malloc0(256); + spd[0] =3D 128; /* data bytes in EEPROM */ + spd[1] =3D 8; /* log2 size of EEPROM */ + spd[2] =3D type; + spd[3] =3D 13; /* row address bits */ + spd[4] =3D 10; /* column address bits */ + spd[5] =3D (type =3D=3D DDR2 ? nbanks - 1 : nbanks); + spd[6] =3D 64; /* module data width */ + /* reserved / data width high */ + spd[8] =3D 4; /* interface voltage level */ + spd[9] =3D 0x25; /* highest CAS latency */ + spd[10] =3D 1; /* access time */ + /* DIMM configuration 0 =3D non-ECC */ + spd[12] =3D 0x82; /* refresh requirements */ + spd[13] =3D 8; /* primary SDRAM width */ + /* ECC SDRAM width */ + spd[15] =3D (type =3D=3D DDR2 ? 0 : 1); /* reserved / delay for random= col rd */ + spd[16] =3D 12; /* burst lengths supported */ + spd[17] =3D 4; /* banks per SDRAM device */ + spd[18] =3D 12; /* ~CAS latencies supported */ + spd[19] =3D (type =3D=3D DDR2 ? 0 : 1); /* reserved / ~CS latencies su= pported */ + spd[20] =3D 2; /* DIMM type / ~WE latencies */ + /* module features */ + /* memory chip features */ + spd[23] =3D 0x12; /* clock cycle time @ medium CAS latency */ + /* data access time */ + /* clock cycle time @ short CAS latency */ + /* data access time */ + spd[27] =3D 20; /* min. row precharge time */ + spd[28] =3D 15; /* min. row active row delay */ + spd[29] =3D 20; /* min. ~RAS to ~CAS delay */ + spd[30] =3D 45; /* min. active to precharge time */ + spd[31] =3D density; + spd[32] =3D 20; /* addr/cmd setup time */ + spd[33] =3D 8; /* addr/cmd hold time */ + spd[34] =3D 20; /* data input setup time */ + spd[35] =3D 8; /* data input hold time */ + + /* checksum */ + for (i =3D 0; i < 63; i++) { + spd[63] +=3D spd[i]; + } + return spd; +} diff --git a/include/hw/i2c/smbus.h b/include/hw/i2c/smbus.h index d8b1b9ee81..0adc2991b5 100644 --- a/include/hw/i2c/smbus.h +++ b/include/hw/i2c/smbus.h @@ -93,4 +93,7 @@ void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address= , uint8_t *eeprom_buf); void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, const uint8_t *eeprom_spd, int size); =20 +enum sdram_type { SDR =3D 0x4, DDR =3D 0x7, DDR2 =3D 0x8 }; +uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t size); + #endif --=20 2.13.7