From nobody Tue Feb 10 02:01:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu ARC-Seal: i=1; a=rsa-sha256; t=1612138987; cv=none; d=zohomail.com; s=zohoarc; b=fe8jc+H5eRlaH51KAZW3yvtrgy/JdoAkCZhZ6lhvctPZqIM0pxAcXbMHCIxjDKm0GXOjMDKgxA+39NsBYf+tayB7zIe4DZa1HHMuU8tvEayB6/EFtN2imKCmg7aZzTxynmeTM/bptAfO8NrVpbvSn7tV+07mEn3lN1IGwNGTZuU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612138987; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6FBwEJM0z0ds9AOlOLS0O2DXGCa6xfqH3ng1If1jVWs=; b=Yyo2RgXFMKMM/6zflVJiZk8C6XBziP/S+GdqL6BX22fsBxDX00kdf5+rOfF4rvE3UJWeqcXJmlu4Pn9kJZYrUxGGp+0+zskAsrkvAIX9fgD9JhuicdBphar6wM6lvkwVoHoYK16TY3lwMlIGA/L5g066NCCo2LqSVxzHmJ4wsjM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612138987468170.3078323353625; Sun, 31 Jan 2021 16:23:07 -0800 (PST) Received: from localhost ([::1]:47470 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6Mzi-00068Q-DC for importer@patchew.org; Sun, 31 Jan 2021 19:23:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Mvh-0001pF-Rd for qemu-devel@nongnu.org; Sun, 31 Jan 2021 19:18:57 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]:34434) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6Mvd-0001AP-0y for qemu-devel@nongnu.org; Sun, 31 Jan 2021 19:18:57 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id C4407746340; Mon, 1 Feb 2021 01:18:44 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 274A5746354; Mon, 1 Feb 2021 01:18:44 +0100 (CET) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 5/6] m68k: MOVEC insn. should generate exception if wrong CR is accessed Date: Mon, 01 Feb 2021 01:01:52 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Lucien Murray-Pitts Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Lucien Murray-Pitts Add CPU class detection for each CR type in the m68k_move_to/from helpers, so that it throws and exception if an unsupported register is requested for that CPU class. Reclassified MOVEC insn. as only supported from 68010. Signed-off-by: Lucien Murray-Pitts Signed-off-by: BALATON Zoltan --- target/m68k/cpu.c | 1 + target/m68k/cpu.h | 1 + target/m68k/helper.c | 188 ++++++++++++++++++++++++++++++---------- target/m68k/translate.c | 2 +- 4 files changed, 146 insertions(+), 46 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5e7aec5b13..31f96df2a2 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -132,6 +132,7 @@ static void m68010_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_M68010); m68k_set_feature(env, M68K_FEATURE_RTD); m68k_set_feature(env, M68K_FEATURE_BKPT); + m68k_set_feature(env, M68K_FEATURE_MOVEC); } =20 /* diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index ae34c94615..5d2cb012e5 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -497,6 +497,7 @@ enum m68k_features { M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */ M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */ M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */ + M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */ }; =20 static inline int m68k_feature(CPUM68KState *env, int feature) diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 69acdc3b35..1efd6e4f65 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -184,6 +184,14 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t r= eg, uint32_t val) } } =20 +static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) +{ + CPUState *cs =3D env_cpu(env); + + cs->exception_index =3D tt; + cpu_loop_exit_restore(cs, raddr); +} + void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) { switch (reg) { @@ -209,61 +217,104 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32= _t reg, uint32_t val) env->cacr =3D val & 0x80008000; } else if (m68k_feature(env, M68K_FEATURE_M68060)) { env->cacr =3D val & 0xf8e0e000; + } else { + break; } m68k_switch_sp(env); return; /* MC680[46]0 */ case M68K_CR_TC: - env->mmu.tcr =3D val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->mmu.tcr =3D val; + return; + } + break; /* MC68040 */ case M68K_CR_MMUSR: - env->mmu.mmusr =3D val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.mmusr =3D val; + return; + } + break; /* MC680[46]0 */ case M68K_CR_SRP: - env->mmu.srp =3D val; - return; - case M68K_CR_URP: - env->mmu.urp =3D val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->mmu.srp =3D val; + return; + } + break; /* MC680[46]0 */ + case M68K_CR_URP: + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->mmu.urp =3D val; + return; + } + break; + /* MC680[12346]0 */ case M68K_CR_USP: env->sp[M68K_USP] =3D val; return; /* MC680[234]0 */ case M68K_CR_MSP: - env->sp[M68K_SSP] =3D val; - return; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + env->sp[M68K_SSP] =3D val; + return; + } + break; /* MC680[234]0 */ case M68K_CR_ISP: - env->sp[M68K_ISP] =3D val; - return; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + env->sp[M68K_ISP] =3D val; + return; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_ITT0: - env->mmu.ttr[M68K_ITTR0] =3D val; - return; + case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_ITTR0] =3D val; + return; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_ITT1: - env->mmu.ttr[M68K_ITTR1] =3D val; - return; + case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_ITTR1] =3D val; + return; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_DTT0: - env->mmu.ttr[M68K_DTTR0] =3D val; - return; + case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_DTTR0] =3D val; + return; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_DTT1: - env->mmu.ttr[M68K_DTTR1] =3D val; - return; + case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_DTTR1] =3D val; + return; + } + break; /* Unimplemented Registers */ case M68K_CR_CAAR: case M68K_CR_PCR: case M68K_CR_BUSCR: - break; + cpu_abort(env_cpu(env), + "Unimplemented control register write 0x%x =3D 0x%x\n", + reg, val); } - cpu_abort(env_cpu(env), - "Unimplemented control register write 0x%x =3D 0x%x\n", - reg, val); + + /* Invalid control registers will generate an exception. */ + raise_exception_ra(env, EXCP_ILLEGAL, 0); + return; } =20 uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) @@ -280,48 +331,95 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, u= int32_t reg) return env->vbr; /* MC680[2346]0 */ case M68K_CR_CACR: - return env->cacr; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->cacr; + } + break; /* MC680[46]0 */ case M68K_CR_TC: - return env->mmu.tcr; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->mmu.tcr; + } + break; /* MC68040 */ case M68K_CR_MMUSR: - return env->mmu.mmusr; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.mmusr; + } + break; /* MC680[46]0 */ case M68K_CR_SRP: - return env->mmu.srp; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->mmu.srp; + } + break; + /* MC68040/MC68LC040 */ + case M68K_CR_URP: + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->mmu.urp; + } + break; /* MC680[46]0 */ case M68K_CR_USP: return env->sp[M68K_USP]; /* MC680[234]0 */ case M68K_CR_MSP: - return env->sp[M68K_SSP]; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + return env->sp[M68K_SSP]; + } + break; /* MC680[234]0 */ case M68K_CR_ISP: - return env->sp[M68K_ISP]; - /* MC68040/MC68LC040 */ - case M68K_CR_URP: - return env->mmu.urp; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + return env->sp[M68K_ISP]; + } + break; /* MC68040/MC68LC040 */ case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */ - return env->mmu.ttr[M68K_ITTR0]; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_ITTR0]; + } + break; /* MC68040/MC68LC040 */ case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */ - return env->mmu.ttr[M68K_ITTR1]; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_ITTR1]; + } + break; /* MC68040/MC68LC040 */ case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */ - return env->mmu.ttr[M68K_DTTR0]; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_DTTR0]; + } + break; /* MC68040/MC68LC040 */ case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */ - return env->mmu.ttr[M68K_DTTR1]; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_DTTR1]; + } + break; /* Unimplemented Registers */ case M68K_CR_CAAR: case M68K_CR_PCR: case M68K_CR_BUSCR: - break; + cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\= n", + reg); } - cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n", - reg); + + /* Invalid control registers will generate an exception. */ + raise_exception_ra(env, EXCP_ILLEGAL, 0); + + return 0; } =20 void HELPER(set_macsr)(CPUM68KState *env, uint32_t val) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 133a404919..ac936ebe8f 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6010,7 +6010,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(stop, 4e72, ffff); BASE(rte, 4e73, ffff); INSN(cf_movec, 4e7b, ffff, CF_ISA_A); - INSN(m68k_movec, 4e7a, fffe, M68000); + INSN(m68k_movec, 4e7a, fffe, MOVEC); #endif BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); --=20 2.21.3