From nobody Wed Nov 27 19:33:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1697645426; cv=none; d=zohomail.com; s=zohoarc; b=b2i0/26YzC3olzR7xULTL52X/cq+4snbJ9Ozzjzut+IPjbv7tD9IpqDRHCWbLGq5MlQl3tRf6SSvWpPzxt7fQyvLT6uYqJLFLui08gDQDLZs0S9hu9JE4VA/l/G21hYLhg3M/F1CD4hxCAUWTFetHgIK5eJFobtjY7to9tBmctI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697645426; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8ZNVaGsAOPPhl+5mNLWULAc38++TrKNMAMlYSymFqYg=; b=QjF/eXQ9PPZBW/2Xs9ks4eTZ1Dr9DLUWS1Gp/QHhdd2kDKNFYcp6tw2m67fpjEv9oajkFdrnx8ILEfxUPEL63ZOiVESFHI5SeABpO0Z59nsnMdFnBWDuSRtbT7Vr0gJWbCuJ6uI9in/tCYS+9hQptNAwh8vSU87mvIJ76zdInbw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697645426911207.03846674932788; Wed, 18 Oct 2023 09:10:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qt8x3-0001dP-V6; Wed, 18 Oct 2023 11:59:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qt8vc-0007wL-KW for qemu-devel@nongnu.org; Wed, 18 Oct 2023 11:57:51 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qt8va-0007LZ-Kx for qemu-devel@nongnu.org; Wed, 18 Oct 2023 11:57:48 -0400 Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-615-q2GpbHASPo2Pae6zAKeK_w-1; Wed, 18 Oct 2023 11:57:44 -0400 Received: by mail-wm1-f72.google.com with SMTP id 5b1f17b1804b1-406de77fb85so44713575e9.0 for ; Wed, 18 Oct 2023 08:57:44 -0700 (PDT) Received: from redhat.com ([2a02:14f:1f2:2037:f34:d61b:7da0:a7be]) by smtp.gmail.com with ESMTPSA id c16-20020a05600c0ad000b003fee567235bsm1998934wmr.1.2023.10.18.08.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 08:57:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1697644665; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=8ZNVaGsAOPPhl+5mNLWULAc38++TrKNMAMlYSymFqYg=; b=HbciJyF5DpyFi4bZfav1J7I7Z7RkgmRfrLf5jjjkQirHcwUvDMahLzcFF9Y5AW+7UtRAbh viULdaKF2tRjfZo7CyF3yLx/tKSKZQPWXcRt32NPRAFwaF/Xx3z8vzMJiMmPXHv6QyMNAl FpyDdSne0mb1ggKydPt3vSCAKMr2nn8= X-MC-Unique: q2GpbHASPo2Pae6zAKeK_w-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697644662; x=1698249462; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=8ZNVaGsAOPPhl+5mNLWULAc38++TrKNMAMlYSymFqYg=; b=PP7FU7ej8giAtsz1bzM2DjJ9MJoBGNUpPN4yIGUIgWQ0F7hWceHBvM4KFyqH9H8Zw3 uxRAqHiFy4rFG/odGtIb/4ZaBq1pDN40cBvsB+NYIR3auIMDsMuW7UYhU166Kg9YMtaH 1nkXQeIlwQ1im9mE1Qv5I7XVL4bNJEPUHWzhjivd6hPDLtMy+LFrdm1IiWVsLDJzhBwi KaBQ5z4RP93/l7SUOUgF0YRN5tjbmGmfFwYXSffCUWCe/ur1gVDbVGZDScHTfvLOuYkF x9wSUW5lNsKLIhREphCyxbZ9Zui1bd/Mks73uJLum4pVe/c2bwB85OOIosJBLYJMxja9 ctFw== X-Gm-Message-State: AOJu0YxHgoDeel2LMqrnk6aMt5dlbqman2LSF2AGM9ArHb9PS8X4QzbI 48GAZflf9WHF8Yca3092uF3kgn+vjN5eSO2lePC41SR11dtDCO29SLX8qq5KZM0YYszh3FDblBn QI0FLyf1DW5F3kG5X/r26e0oHFvKIsw9+yIX9GVi4u/ZS0d8xLReKkz4xypWlsIWpN0EOTL8= X-Received: by 2002:a05:600c:350a:b0:405:a30:151e with SMTP id h10-20020a05600c350a00b004050a30151emr4539337wmq.12.1697644662607; Wed, 18 Oct 2023 08:57:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG65TajzvKOZYETI1pDCfdgg6FB54W0dVrYwhN087VAICwo4y6JRBDODj1Iyag4L7qujr1PIw== X-Received: by 2002:a05:600c:350a:b0:405:a30:151e with SMTP id h10-20020a05600c350a00b004050a30151emr4539317wmq.12.1697644662211; Wed, 18 Oct 2023 08:57:42 -0700 (PDT) Date: Wed, 18 Oct 2023 11:57:38 -0400 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Bernhard Beschow , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Aurelien Jarno , Marcel Apfelbaum , =?utf-8?B?SGVydsOp?= Poussineau Subject: [PULL 56/83] hw/isa/piix3: Drop the "3" from PIIX base class name Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697645427724100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bernhard Beschow TYPE_PIIX3_PCI_DEVICE was the former base class of the Xen and non-Xen vari= ants of the PIIX3 ISA device models. It will become the base class for the PIIX3= and PIIX4 device models, so drop the "3" from the type names. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin Message-Id: <20231007123843.127151-15-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin --- include/hw/southbridge/piix.h | 6 ++-- hw/isa/piix3.c | 56 +++++++++++++++++------------------ 2 files changed, 30 insertions(+), 32 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index c56ce49fd3..0b257e1582 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -71,11 +71,9 @@ struct PIIXState { bool has_usb; bool smm_enabled; }; -typedef struct PIIXState PIIX3State; =20 -#define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, - TYPE_PIIX3_PCI_DEVICE) +#define TYPE_PIIX_PCI_DEVICE "pci-piix" +OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE) =20 #define TYPE_PIIX3_DEVICE "PIIX3" #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 5b867df299..c7e59249b6 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -35,7 +35,7 @@ #include "migration/vmstate.h" #include "hw/acpi/acpi_aml_interface.h" =20 -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) { qemu_set_irq(piix3->isa_irqs_in[pic_irq], !!(piix3->pic_levels & @@ -43,7 +43,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_= irq) (pic_irq * PIIX_NUM_PIRQS)))); } =20 -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int = level) +static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int l= evel) { int pic_irq; uint64_t mask; @@ -58,7 +58,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix= 3, int pirq, int level) piix3->pic_levels |=3D mask * !!level; } =20 -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) { int pic_irq; =20 @@ -74,13 +74,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int = pirq, int level) =20 static void piix3_set_irq(void *opaque, int pirq, int level) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; piix3_set_irq_level(piix3, pirq, level); } =20 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; int irq =3D piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; =20 @@ -95,7 +95,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opa= que, int pin) } =20 /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIX3State *piix3) +static void piix3_update_irq_levels(PIIXState *piix3) { PCIBus *bus =3D pci_get_bus(&piix3->dev); int pirq; @@ -111,7 +111,7 @@ static void piix3_write_config(PCIDevice *dev, { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); int pic_irq; =20 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); @@ -124,7 +124,7 @@ static void piix3_write_config(PCIDevice *dev, =20 static void piix3_reset(DeviceState *dev) { - PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); + PIIXState *d =3D PIIX_PCI_DEVICE(dev); uint8_t *pci_conf =3D d->dev.config; =20 pci_conf[0x04] =3D 0x07; /* master, memory and I/O */ @@ -165,7 +165,7 @@ static void piix3_reset(DeviceState *dev) =20 static int piix3_post_load(void *opaque, int version_id) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; int pirq; =20 /* @@ -188,7 +188,7 @@ static int piix3_post_load(void *opaque, int version_id) static int piix3_pre_save(void *opaque) { int i; - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; =20 for (i =3D 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { piix3->pci_irq_levels_vmstate[i] =3D @@ -200,7 +200,7 @@ static int piix3_pre_save(void *opaque) =20 static bool piix3_rcr_needed(void *opaque) { - PIIX3State *piix3 =3D opaque; + PIIXState *piix3 =3D opaque; =20 return (piix3->rcr !=3D 0); } @@ -211,7 +211,7 @@ static const VMStateDescription vmstate_piix3_rcr =3D { .minimum_version_id =3D 1, .needed =3D piix3_rcr_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT8(rcr, PIIX3State), + VMSTATE_UINT8(rcr, PIIXState), VMSTATE_END_OF_LIST() } }; @@ -223,8 +223,8 @@ static const VMStateDescription vmstate_piix3 =3D { .post_load =3D piix3_post_load, .pre_save =3D piix3_pre_save, .fields =3D (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX3State), - VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState, PIIX_NUM_PIRQS, 3), VMSTATE_END_OF_LIST() }, @@ -237,7 +237,7 @@ static const VMStateDescription vmstate_piix3 =3D { =20 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned le= n) { - PIIX3State *d =3D opaque; + PIIXState *d =3D opaque; =20 if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -248,7 +248,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64= _t val, unsigned len) =20 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) { - PIIX3State *d =3D opaque; + PIIXState *d =3D opaque; =20 return d->rcr; } @@ -265,7 +265,7 @@ static const MemoryRegionOps rcr_ops =3D { =20 static void pci_piix3_realize(PCIDevice *dev, Error **errp) { - PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); + PIIXState *d =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; uint32_t irq; @@ -345,7 +345,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *= scope) =20 static void pci_piix3_init(Object *obj) { - PIIX3State *d =3D PIIX3_PCI_DEVICE(obj); + PIIXState *d =3D PIIX_PCI_DEVICE(obj); =20 qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs", ISA_NUM_IRQS); @@ -355,10 +355,10 @@ static void pci_piix3_init(Object *obj) } =20 static Property pci_piix3_props[] =3D { - DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), - DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -386,10 +386,10 @@ static void pci_piix3_class_init(ObjectClass *klass, = void *data) adevc->build_dev_aml =3D build_pci_isa_aml; } =20 -static const TypeInfo piix3_pci_type_info =3D { - .name =3D TYPE_PIIX3_PCI_DEVICE, +static const TypeInfo piix_pci_type_info =3D { + .name =3D TYPE_PIIX_PCI_DEVICE, .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PIIX3State), + .instance_size =3D sizeof(PIIXState), .instance_init =3D pci_piix3_init, .abstract =3D true, .class_init =3D pci_piix3_class_init, @@ -403,7 +403,7 @@ static const TypeInfo piix3_pci_type_info =3D { static void piix3_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 =3D PIIX_PCI_DEVICE(dev); PCIBus *pci_bus =3D pci_get_bus(dev); =20 pci_piix3_realize(dev, errp); @@ -424,13 +424,13 @@ static void piix3_class_init(ObjectClass *klass, void= *data) =20 static const TypeInfo piix3_info =3D { .name =3D TYPE_PIIX3_DEVICE, - .parent =3D TYPE_PIIX3_PCI_DEVICE, + .parent =3D TYPE_PIIX_PCI_DEVICE, .class_init =3D piix3_class_init, }; =20 static void piix3_register_types(void) { - type_register_static(&piix3_pci_type_info); + type_register_static(&piix_pci_type_info); type_register_static(&piix3_info); } =20 --=20 MST