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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Suravee Suthikulpanit , Alejandro Jimenez , Santosh Shukla , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL 31/65] amd_iommu: Send notification when invalidate interrupt entry cache Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1730754794843116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Suravee Suthikulpanit In order to support AMD IOMMU interrupt remapping emulation with PCI pass-through devices, QEMU needs to notify VFIO when guest IOMMU driver updates and invalidate the guest interrupt remapping table (IRT), and communicate information so that the host IOMMU driver can update the shadowed interrupt remapping table in the host IOMMU. Therefore, send notification when guest IOMMU emulates the IRT invalidation commands. Reviewed-by: Alejandro Jimenez Signed-off-by: Suravee Suthikulpanit Signed-off-by: Santosh Shukla Message-Id: <20240927172913.121477-5-santosh.shukla@amd.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/amd_iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 9b923f6eb4..38297376e7 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -431,6 +431,12 @@ static void amdvi_complete_ppr(AMDVIState *s, uint64_t= *cmd) trace_amdvi_ppr_exec(); } =20 +static void amdvi_intremap_inval_notify_all(AMDVIState *s, bool global, + uint32_t index, uint32_t mask) +{ + x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask); +} + static void amdvi_inval_all(AMDVIState *s, uint64_t *cmd) { if (extract64(cmd[0], 0, 60) || cmd[1]) { @@ -438,6 +444,9 @@ static void amdvi_inval_all(AMDVIState *s, uint64_t *cm= d) s->cmdbuf + s->cmdbuf_head); } =20 + /* Notify global invalidation */ + amdvi_intremap_inval_notify_all(s, true, 0, 0); + amdvi_iotlb_reset(s); trace_amdvi_all_inval(); } @@ -486,6 +495,9 @@ static void amdvi_inval_inttable(AMDVIState *s, uint64_= t *cmd) return; } =20 + /* Notify global invalidation */ + amdvi_intremap_inval_notify_all(s, true, 0, 0); + trace_amdvi_intr_inval(); } =20 --=20 MST