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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 65 +++++++++++++++++++++++++++++++++------ 1 file changed, 55 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1b747abf93..2c6d2bc3a3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -641,6 +641,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + target_ulong s; =20 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide * so we mask off the MSB and separate into trap type and cause. @@ -650,13 +651,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong deleg =3D async ? env->mideleg : env->medeleg; target_ulong tval =3D 0; =20 - static const int ecall_cause_map[] =3D { - [PRV_U] =3D RISCV_EXCP_U_ECALL, - [PRV_S] =3D RISCV_EXCP_S_ECALL, - [PRV_H] =3D RISCV_EXCP_VS_ECALL, - [PRV_M] =3D RISCV_EXCP_M_ECALL - }; - if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { @@ -680,7 +674,16 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* ecall is dispatched as one cause so translate based on mode */ if (cause =3D=3D RISCV_EXCP_U_ECALL) { assert(env->priv <=3D 3); - cause =3D ecall_cause_map[env->priv]; + + if (env->priv =3D=3D PRV_M) { + cause =3D RISCV_EXCP_M_ECALL; + } else if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(en= v)) { + cause =3D RISCV_EXCP_VS_ECALL; + } else if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(e= nv)) { + cause =3D RISCV_EXCP_S_ECALL; + } else if (env->priv =3D=3D PRV_U) { + cause =3D RISCV_EXCP_U_ECALL; + } } } =20 @@ -690,7 +693,36 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (env->priv <=3D PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { /* handle the trap in S-mode */ - target_ulong s =3D *env->mstatus; + if (riscv_has_ext(env, RVH)) { + target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; + + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && + !riscv_cpu_force_hs_excep_enabled(env)) { + /* Trap to VS mode */ + } else if (riscv_cpu_virt_enabled(env)) { + /* Trap into HS mode, from virt */ + riscv_cpu_swap_hypervisor_regs(env); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2V, + get_field(env->hstatus, HSTATUS_S= PV)); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2P, + get_field(*env->mstatus, SSTATUS_= SPP)); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, + riscv_cpu_virt_enabled(env)); + + riscv_cpu_set_virt_enabled(env, 0); + riscv_cpu_set_force_hs_excep(env, 0); + } else { + /* Trap into HS mode */ + env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2V, + get_field(env->hstatus, HSTATUS_S= PV)); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2P, + get_field(*env->mstatus, SSTATUS_= SPP)); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, + riscv_cpu_virt_enabled(env)); + } + } + + s =3D *env->mstatus; s =3D set_field(s, MSTATUS_SPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_SPP, env->priv); @@ -704,7 +736,20 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_mode(env, PRV_S); } else { /* handle the trap in M-mode */ - target_ulong s =3D *env->mstatus; + if (riscv_has_ext(env, RVH)) { + if (riscv_cpu_virt_enabled(env)) { + riscv_cpu_swap_hypervisor_regs(env); + } + *env->mstatus =3D set_field(*env->mstatus, MSTATUS_MPV, + riscv_cpu_virt_enabled(env)); + *env->mstatus =3D set_field(*env->mstatus, MSTATUS_MTL, + riscv_cpu_force_hs_excep_enabled(env= )); + + /* Trapping to M mode, virt is disabled */ + riscv_cpu_set_virt_enabled(env, 0); + } + + s =3D *env->mstatus; s =3D set_field(s, MSTATUS_MPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_MPP, env->priv); --=20 2.24.0