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Sun, 19 Oct 2025 17:16:50 +0200 (CEST) Received: (qmail 23451 invoked by uid 990); 19 Oct 2025 15:16:50 -0000 Received: from unknown (HELO unkown) (::1) by skiff.uberspace.de (Haraka/3.0.1) with ESMTPSA; Sun, 19 Oct 2025 17:16:46 +0200 Authentication-Results: skiff.uberspace.de; auth=pass (plain) From: Julian Ganz To: qemu-devel@nongnu.org Cc: Julian Ganz , Daniel Henrique Barboza , Alistair Francis , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v8 16/25] target/riscv: call plugin trap callbacks Date: Sun, 19 Oct 2025 17:15:05 +0200 Message-ID: X-Mailer: git-send-email 2.49.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Bar: ----- X-Rspamd-Report: REPLY(-4) BAYES_HAM(-2.999754) MID_CONTAINS_FROM(1) MIME_GOOD(-0.1) R_MISSING_CHARSET(0.5) X-Rspamd-Score: -5.599754 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nut.email; s=uberspace; h=from:to:cc:subject:date; bh=6jnG3wDchPvR9iC7OeKM71ZvHzTjOj/B4aMwSwCZlYo=; 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charset="utf-8" We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for RISC-V targets. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Julian Ganz --- target/riscv/cpu_helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3479a62cc7..10a10dcd90 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -36,6 +36,7 @@ #include "cpu_bits.h" #include "debug.h" #include "pmp.h" +#include "qemu/plugin.h" =20 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { @@ -2176,6 +2177,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; const bool prev_virt =3D env->virt_enabled; const target_ulong prev_priv =3D env->priv; + uint64_t last_pc =3D env->pc; target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -2198,6 +2200,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_SEMIHOST: do_common_semihosting(cs); env->pc +=3D 4; + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; #endif case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: @@ -2467,6 +2470,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) prev_priv, prev_virt); } =20 + if (async) { + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); + } else { + qemu_plugin_vcpu_exception_cb(cs, last_pc); + } + /* * Interrupt/exception/trap delivery is asynchronous event and as per * zicfilp spec CPU should clear up the ELP state. No harm in clearing --=20 2.49.1