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[109.242.226.170]) by smtp.gmail.com with ESMTPSA id m8-20020adfa3c8000000b0032d7fde2d3csm7990663wrb.79.2023.10.13.00.49.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 00:49:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697183390; x=1697788190; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7aeKq35mmTIUN+fGFa1jZeWofe0W3T+gZsntbEXTBh4=; b=e537+jo095yFNGGYePbCeIO8obd985iXi0Mu1/A/hneH9sjRf+9+zjAjis+98qTLN8 CENS9jLEcqW9jHZo4XYt+VUNz/rwpVj887erGfLq94llWxyXR5cvS3Y0Zvf7Rv+g24vk XCT4HxhKGj/uxQDoVDIx3t8Gd+Hd3uqDSoGJxq1Po9bB/Cvx57zHoZt+3MrYAOzXTOpQ qvF4bEqhag7Q/w3EYggmllNeLfxCmw0k7yFVGa6puoOhsZU66kQI6sBiasvwlJO5R8PK Zx6f9/AoiYFkgMk5jRuWMX7YoazxKKUjZWniTucwCCer8YEfXkPbOHvqlHStpOk73eJw Y7bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697183390; x=1697788190; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7aeKq35mmTIUN+fGFa1jZeWofe0W3T+gZsntbEXTBh4=; b=bHZ5gwnfms0nPjUL9AX+QY2FWc4ndoBUMxCSoZE2vH8Sgk0ozp8LWmJlgyAraa5jzm SDgSeEyA7pc3s76RA6ztLTmS9iKOoKrMfkN1mXe0c98xH+7pdC1U/k7/F569GTOP87hU UzMBw2FOTd7z9XNwJqPh3gWGNGIY0H/wdpiqBl2T4kQEXZcrD2wZcfWTzwBl7nB/x5ls dziJmk19GH5E1FWsZnH0k0QYSo67ZIMzmDRvLzUDuHIkNa37qz7a5EPWLliV116VY4jE BuXpjkZSqfHal3mBfiBcdbZyI9unrhvZcNQwNfaMo2B+JaUAEDj0cp/1AA9fC/GBGzlo gN5g== X-Gm-Message-State: AOJu0Yx+RoG6AGbQTQZqOS1zz0RommmHXRH80nIiZe26e3/HZWyYTzv/ vKmri60OgAD/QEb50jjcHHjkDNLNcJFR1G9T1hE= X-Google-Smtp-Source: AGHT+IFELsz3uCt0tiTm+VEqnfXz+EDHiO9BNF6vnJTsWChhcLiftpgY6NUn4jcUngww3YefDO7x3A== X-Received: by 2002:a05:6000:1cc:b0:32d:819c:5da6 with SMTP id t12-20020a05600001cc00b0032d819c5da6mr6967311wrx.21.1697183390123; Fri, 13 Oct 2023 00:49:50 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org Cc: Emmanouil Pitsidianakis , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH 03/78] fpu/softfloat: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:47:07 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697183731386100002 Content-Type: text/plain; charset="utf-8" In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- fpu/softfloat-parts.c.inc | 8 ++++---- fpu/softfloat.c | 7 ++++--- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a44649f4f4..df64cc7a29 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -138,166 +138,166 @@ static void partsN(canonicalize)(FloatPartsN *p, fl= oat_status *status, /* * Round and uncanonicalize a floating-point number by parts. There * are FRAC_SHIFT bits that may require rounding at the bottom of the * fraction; these bits will be removed. The exponent will be biased * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. */ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, const FloatFmt *fmt) { const int exp_max =3D fmt->exp_max; const int frac_shift =3D fmt->frac_shift; const uint64_t round_mask =3D fmt->round_mask; const uint64_t frac_lsb =3D round_mask + 1; const uint64_t frac_lsbm1 =3D round_mask ^ (round_mask >> 1); const uint64_t roundeven_mask =3D round_mask | frac_lsb; uint64_t inc; bool overflow_norm =3D false; int exp, flags =3D 0; =20 switch (s->float_rounding_mode) { case float_round_nearest_even: if (N > 64 && frac_lsb =3D=3D 0) { inc =3D ((p->frac_hi & 1) || (p->frac_lo & round_mask) !=3D fr= ac_lsbm1 ? frac_lsbm1 : 0); } else { inc =3D ((p->frac_lo & roundeven_mask) !=3D frac_lsbm1 ? frac_lsbm1 : 0); } break; case float_round_ties_away: inc =3D frac_lsbm1; break; case float_round_to_zero: overflow_norm =3D true; inc =3D 0; break; case float_round_up: inc =3D p->sign ? 0 : round_mask; overflow_norm =3D p->sign; break; case float_round_down: inc =3D p->sign ? round_mask : 0; overflow_norm =3D !p->sign; break; case float_round_to_odd: overflow_norm =3D true; - /* fall through */ + fallthrough; case float_round_to_odd_inf: if (N > 64 && frac_lsb =3D=3D 0) { inc =3D p->frac_hi & 1 ? 0 : round_mask; } else { inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; } break; default: g_assert_not_reached(); } =20 exp =3D p->exp + fmt->exp_bias; if (likely(exp > 0)) { if (p->frac_lo & round_mask) { flags |=3D float_flag_inexact; if (frac_addi(p, p, inc)) { frac_shr(p, 1); p->frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; exp++; } p->frac_lo &=3D ~round_mask; } =20 if (fmt->arm_althp) { /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ if (unlikely(exp > exp_max)) { /* Overflow. Return the maximum normal. */ flags =3D float_flag_invalid; exp =3D exp_max; frac_allones(p); p->frac_lo &=3D ~round_mask; } } else if (unlikely(exp >=3D exp_max)) { flags |=3D float_flag_overflow; if (s->rebias_overflow) { exp -=3D fmt->exp_re_bias; } else if (overflow_norm) { flags |=3D float_flag_inexact; exp =3D exp_max - 1; frac_allones(p); p->frac_lo &=3D ~round_mask; } else { flags |=3D float_flag_inexact; p->cls =3D float_class_inf; exp =3D exp_max; frac_clear(p); } } frac_shr(p, frac_shift); } else if (unlikely(s->rebias_underflow)) { flags |=3D float_flag_underflow; exp +=3D fmt->exp_re_bias; if (p->frac_lo & round_mask) { flags |=3D float_flag_inexact; if (frac_addi(p, p, inc)) { frac_shr(p, 1); p->frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; exp++; } p->frac_lo &=3D ~round_mask; } frac_shr(p, frac_shift); } else if (s->flush_to_zero) { flags |=3D float_flag_output_denormal; p->cls =3D float_class_zero; exp =3D 0; frac_clear(p); } else { bool is_tiny =3D s->tininess_before_rounding || exp < 0; =20 if (!is_tiny) { FloatPartsN discard; is_tiny =3D !frac_addi(&discard, p, inc); } =20 frac_shrjam(p, !fmt->m68k_denormal - exp); =20 if (p->frac_lo & round_mask) { /* Need to recompute round-to-even/round-to-odd. */ switch (s->float_rounding_mode) { case float_round_nearest_even: if (N > 64 && frac_lsb =3D=3D 0) { inc =3D ((p->frac_hi & 1) || (p->frac_lo & round_mask) !=3D frac_lsbm1 ? frac_lsbm1 : 0); } else { inc =3D ((p->frac_lo & roundeven_mask) !=3D frac_lsbm1 ? frac_lsbm1 : 0); } break; case float_round_to_odd: case float_round_to_odd_inf: if (N > 64 && frac_lsb =3D=3D 0) { inc =3D p->frac_hi & 1 ? 0 : round_mask; } else { inc =3D p->frac_lo & frac_lsb ? 0 : round_mask; } break; default: break; } flags |=3D float_flag_inexact; frac_addi(p, p, inc); p->frac_lo &=3D ~round_mask; } =20 exp =3D (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) && !fmt->m68k_denor= mal; frac_shr(p, frac_shift); =20 if (is_tiny && (flags & float_flag_inexact)) { flags |=3D float_flag_underflow; } if (exp =3D=3D 0 && frac_eqz(p)) { p->cls =3D float_class_zero; } } p->exp =3D exp; float_raise(flags, s); } @@ -1051,219 +1051,219 @@ static void partsN(round_to_int)(FloatPartsN *a, = FloatRoundMode rmode, /* * Returns the result of converting the floating-point value `a' to * the two's complement integer format. The conversion is performed * according to the IEC/IEEE Standard for Binary Floating-Point * Arithmetic---which means in particular that the conversion is * rounded according to the current rounding mode. If `a' is a NaN, * the largest positive integer is returned. Otherwise, if the * conversion overflows, the largest integer with the same sign as `a' * is returned. */ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, int scale, int64_t min, int64_t max, float_status *s) { int flags =3D 0; uint64_t r; =20 switch (p->cls) { case float_class_snan: flags |=3D float_flag_invalid_snan; - /* fall through */ + fallthrough; case float_class_qnan: flags |=3D float_flag_invalid; r =3D max; break; =20 case float_class_inf: flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D p->sign ? min : max; break; =20 case float_class_zero: return 0; =20 case float_class_normal: /* TODO: N - 2 is frac_size for rounding; could use input fmt. */ if (parts_round_to_int_normal(p, rmode, scale, N - 2)) { flags =3D float_flag_inexact; } =20 if (p->exp <=3D DECOMPOSED_BINARY_POINT) { r =3D p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); } else { r =3D UINT64_MAX; } if (p->sign) { if (r <=3D -(uint64_t)min) { r =3D -r; } else { flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D min; } } else if (r > max) { flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D max; } break; =20 default: g_assert_not_reached(); } =20 float_raise(flags, s); return r; } =20 /* * Returns the result of converting the floating-point value `a' to * the unsigned integer format. The conversion is performed according * to the IEC/IEEE Standard for Binary Floating-Point * Arithmetic---which means in particular that the conversion is * rounded according to the current rounding mode. If `a' is a NaN, * the largest unsigned integer is returned. Otherwise, if the * conversion overflows, the largest unsigned integer is returned. If * the 'a' is negative, the result is rounded and zero is returned; * values that do not round to zero will raise the inexact exception * flag. */ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode, int scale, uint64_t max, float_statu= s *s) { int flags =3D 0; uint64_t r; =20 switch (p->cls) { case float_class_snan: flags |=3D float_flag_invalid_snan; - /* fall through */ + fallthrough; case float_class_qnan: flags |=3D float_flag_invalid; r =3D max; break; =20 case float_class_inf: flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D p->sign ? 0 : max; break; =20 case float_class_zero: return 0; =20 case float_class_normal: /* TODO: N - 2 is frac_size for rounding; could use input fmt. */ if (parts_round_to_int_normal(p, rmode, scale, N - 2)) { flags =3D float_flag_inexact; if (p->cls =3D=3D float_class_zero) { r =3D 0; break; } } =20 if (p->sign) { flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D 0; } else if (p->exp > DECOMPOSED_BINARY_POINT) { flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D max; } else { r =3D p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); if (r > max) { flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D max; } } break; =20 default: g_assert_not_reached(); } =20 float_raise(flags, s); return r; } =20 /* * Like partsN(float_to_sint), except do not saturate the result. * Instead, return the rounded unbounded precision two's compliment result, * modulo 2**(bitsm1 + 1). */ static int64_t partsN(float_to_sint_modulo)(FloatPartsN *p, FloatRoundMode rmode, int bitsm1, float_status *s) { int flags =3D 0; uint64_t r; bool overflow =3D false; =20 switch (p->cls) { case float_class_snan: flags |=3D float_flag_invalid_snan; - /* fall through */ + fallthrough; case float_class_qnan: flags |=3D float_flag_invalid; r =3D 0; break; =20 case float_class_inf: overflow =3D true; r =3D 0; break; =20 case float_class_zero: return 0; =20 case float_class_normal: /* TODO: N - 2 is frac_size for rounding; could use input fmt. */ if (parts_round_to_int_normal(p, rmode, 0, N - 2)) { flags =3D float_flag_inexact; } =20 if (p->exp <=3D DECOMPOSED_BINARY_POINT) { /* * Because we rounded to integral, and exp < 64, * we know frac_low is zero. */ r =3D p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); if (p->exp < bitsm1) { /* Result in range. */ } else if (p->exp =3D=3D bitsm1) { /* The only in-range value is INT_MIN. */ overflow =3D !p->sign || p->frac_hi !=3D DECOMPOSED_IMPLIC= IT_BIT; } else { overflow =3D true; } } else { /* Overflow, but there might still be bits to return. */ int shl =3D p->exp - DECOMPOSED_BINARY_POINT; if (shl < N) { frac_shl(p, shl); r =3D p->frac_hi; } else { r =3D 0; } overflow =3D true; } =20 if (p->sign) { r =3D -r; } break; =20 default: g_assert_not_reached(); } =20 if (overflow) { flags =3D float_flag_invalid | float_flag_invalid_cvti; } float_raise(flags, s); return r; } =20 /* * Integer to float conversions * * Returns the result of converting the two's complement integer `a' * to the floating-point format. The conversion is performed according * to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. */ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 027a8e576d..e16e1896ee 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1811,56 +1811,57 @@ static bool floatx80_unpack_canonical(FloatParts128= *p, floatx80 f, static floatx80 floatx80_round_pack_canonical(FloatParts128 *p, float_status *s) { const FloatFmt *fmt =3D &floatx80_params[s->floatx80_rounding_precisio= n]; uint64_t frac; int exp; =20 switch (p->cls) { case float_class_normal: if (s->floatx80_rounding_precision =3D=3D floatx80_precision_x) { parts_uncanon_normal(p, s, fmt); frac =3D p->frac_hi; exp =3D p->exp; } else { FloatParts64 p64; =20 p64.sign =3D p->sign; p64.exp =3D p->exp; frac_truncjam(&p64, p); parts_uncanon_normal(&p64, s, fmt); frac =3D p64.frac; exp =3D p64.exp; } if (exp !=3D fmt->exp_max) { break; } /* rounded to inf -- fall through to set frac correctly */ + fallthrough; =20 case float_class_inf: /* x86 and m68k differ in the setting of the integer bit. */ frac =3D floatx80_infinity_low; exp =3D fmt->exp_max; break; =20 case float_class_zero: frac =3D 0; exp =3D 0; break; =20 case float_class_snan: case float_class_qnan: /* NaNs have the integer bit set. */ frac =3D p->frac_hi | (1ull << 63); exp =3D fmt->exp_max; break; =20 default: g_assert_not_reached(); } =20 return packFloatx80(p->sign, exp, frac); } =20 /* * Addition and subtraction */ @@ -2668,35 +2669,35 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float= _status *status) static void parts_float_to_ahp(FloatParts64 *a, float_status *s) { switch (a->cls) { case float_class_snan: float_raise(float_flag_invalid_snan, s); - /* fall through */ + fallthrough; case float_class_qnan: /* * There is no NaN in the destination format. Raise Invalid * and return a zero with the sign of the input NaN. */ float_raise(float_flag_invalid, s); a->cls =3D float_class_zero; break; =20 case float_class_inf: /* * There is no Inf in the destination format. Raise Invalid * and return the maximum normal with the correct sign. */ float_raise(float_flag_invalid, s); a->cls =3D float_class_normal; a->exp =3D float16_params_ahp.exp_max; a->frac =3D MAKE_64BIT_MASK(float16_params_ahp.frac_shift, float16_params_ahp.frac_size + 1); break; =20 case float_class_normal: case float_class_zero: break; =20 default: g_assert_not_reached(); } } @@ -3190,53 +3191,53 @@ static int64_t float128_to_int64_scalbn(float128 a,= FloatRoundMode rmode, static Int128 float128_to_int128_scalbn(float128 a, FloatRoundMode rmode, int scale, float_status *s) { int flags =3D 0; Int128 r; FloatParts128 p; =20 float128_unpack_canonical(&p, a, s); =20 switch (p.cls) { case float_class_snan: flags |=3D float_flag_invalid_snan; - /* fall through */ + fallthrough; case float_class_qnan: flags |=3D float_flag_invalid; r =3D UINT128_MAX; break; =20 case float_class_inf: flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D p.sign ? INT128_MIN : INT128_MAX; break; =20 case float_class_zero: return int128_zero(); =20 case float_class_normal: if (parts_round_to_int_normal(&p, rmode, scale, 128 - 2)) { flags =3D float_flag_inexact; } =20 if (p.exp < 127) { int shift =3D 127 - p.exp; r =3D int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shi= ft); if (p.sign) { r =3D int128_neg(r); } } else if (p.exp =3D=3D 127 && p.sign && p.frac_lo =3D=3D 0 && p.frac_hi =3D=3D DECOMPOSED_IMPLICIT_BIT) { r =3D INT128_MIN; } else { flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D p.sign ? INT128_MIN : INT128_MAX; } break; =20 default: g_assert_not_reached(); } =20 float_raise(flags, s); return r; } @@ -3617,54 +3618,54 @@ static uint64_t float128_to_uint64_scalbn(float128 = a, FloatRoundMode rmode, static Int128 float128_to_uint128_scalbn(float128 a, FloatRoundMode rmode, int scale, float_status *s) { int flags =3D 0; Int128 r; FloatParts128 p; =20 float128_unpack_canonical(&p, a, s); =20 switch (p.cls) { case float_class_snan: flags |=3D float_flag_invalid_snan; - /* fall through */ + fallthrough; case float_class_qnan: flags |=3D float_flag_invalid; r =3D UINT128_MAX; break; =20 case float_class_inf: flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D p.sign ? int128_zero() : UINT128_MAX; break; =20 case float_class_zero: return int128_zero(); =20 case float_class_normal: if (parts_round_to_int_normal(&p, rmode, scale, 128 - 2)) { flags =3D float_flag_inexact; if (p.cls =3D=3D float_class_zero) { r =3D int128_zero(); break; } } =20 if (p.sign) { flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D int128_zero(); } else if (p.exp <=3D 127) { int shift =3D 127 - p.exp; r =3D int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shi= ft); } else { flags =3D float_flag_invalid | float_flag_invalid_cvti; r =3D UINT128_MAX; } break; =20 default: g_assert_not_reached(); } =20 float_raise(flags, s); return r; } --=20 2.39.2