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Sat, 11 Apr 2026 19:21:30 -0700 (PDT) From: Chao Liu To: Pierrick Bouvier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Cc: qemu-devel@nongnu.org, tangtao1634@phytium.com.cn, devel@lists.libvirt.org, qemu-riscv@nongnu.org Subject: [PATCH v6 5/7] target/riscv: add sdext enter Debug Mode on ebreak Date: Sun, 12 Apr 2026 10:20:22 +0800 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f43; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-qv1-xf43.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1775960548122158500 Content-Type: text/plain; charset="utf-8" RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Route EBREAK via helper_sdext_ebreak. If Sdext is enabled and the matching dcsr.ebreak* bit is set, enter Debug Mode with cause=3Debreak and stop with EXCP_DEBUG. Otherwise keep the normal breakpoint trap. Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Tested-by: Tao Tang --- target/riscv/helper.h | 1 + .../riscv/insn_trans/trans_privileged.c.inc | 6 ++++ target/riscv/op_helper.c | 34 +++++++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c8e76eb116..9538e816f0 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -143,6 +143,7 @@ DEF_HELPER_1(tlb_flush_all, void, env) DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) +DEF_HELPER_2(sdext_ebreak, void, env, tl) #endif =20 /* Hypervisor functions */ diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index f8641b1977..84f0c77513 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -68,9 +68,15 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *= a) if (pre =3D=3D 0x01f01013 && ebreak =3D=3D 0x00100073 && post =3D=3D 0= x40705013) { generate_exception(ctx, RISCV_EXCP_SEMIHOST); } else { +#ifndef CONFIG_USER_ONLY + gen_update_pc(ctx, 0); + gen_helper_sdext_ebreak(tcg_env, tcg_constant_tl(ebreak_addr)); + ctx->base.is_jmp =3D DISAS_NORETURN; +#else tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, offsetof(CPURISCVState, badaddr)); generate_exception(ctx, RISCV_EXCP_BREAKPOINT); +#endif } return true; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ce68ee5959..58d47b88c1 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -456,6 +456,40 @@ target_ulong helper_dret(CPURISCVState *env) #endif } =20 +void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc) +{ + CPUState *cs =3D env_cpu(env); + bool enter_debug =3D false; + + if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode) { + if (env->virt_enabled) { + if (env->priv =3D=3D PRV_S) { + enter_debug =3D env->dcsr & DCSR_EBREAKVS; + } else if (env->priv =3D=3D PRV_U) { + enter_debug =3D env->dcsr & DCSR_EBREAKVU; + } + } else { + if (env->priv =3D=3D PRV_M) { + enter_debug =3D env->dcsr & DCSR_EBREAKM; + } else if (env->priv =3D=3D PRV_S) { + enter_debug =3D env->dcsr & DCSR_EBREAKS; + } else if (env->priv =3D=3D PRV_U) { + enter_debug =3D env->dcsr & DCSR_EBREAKU; + } + } + } + + env->badaddr =3D pc; + + if (enter_debug) { + riscv_cpu_enter_debug_mode(env, pc, DCSR_CAUSE_EBREAK); + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); + } + + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC()); +} + target_ulong helper_mnret(CPURISCVState *env) { target_ulong retpc =3D env->mnepc; --=20 2.53.0