From nobody Sun Nov 24 15:08:06 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63BDC18C937 for ; Thu, 8 Aug 2024 12:26:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723120003; cv=none; b=T/Hz4y7yN4yB87iMPTdTdPpMGFNAQX3B8ZlKdZH9juD5lVqsHGCqw3mPVjIftlMsPMtweI3mtAcOx4oob7oAf51Dw70QoVmzjmRT5+3tNfHBbs9OIkAeCeLA10jiDXhnjPEUfSF7YdaywwDiIJ4xPlA8w4b4gglB5b5Nae4SM/Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723120003; c=relaxed/simple; bh=rEyXbt+nHyXfhaHjwgifZvCFRsjRrNRv8uaioILzvnk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jGGsqCOX7hJQijdjwhU6eu2fKqe0USB8SQe9yn26mFrZRW/G3rjjnfRF4Ds4G7FDh69LZePwV6xrcscszSUqHb0Zr/MjddIpeja4+7/mA6/pZNuWxVng53Qw2a0zhb7fobSHaK4PcookMG157mYKtDmbyPcFmCXXgdtPWN+7G58= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oUFymcJd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oUFymcJd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB218C4AF19; Thu, 8 Aug 2024 12:26:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723120003; bh=rEyXbt+nHyXfhaHjwgifZvCFRsjRrNRv8uaioILzvnk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oUFymcJd+FLhY18BhBN9DZVPJ5JTVDrqAPSAC08ovTReEk4oiVx0HGCueUBlAO2d/ GvY2OIXFCWhWSWSrcR0/IgtcWHeg+GDS5rY+ZnBypCh3mrZnBeF3c4ZiFOkk7ag9VA buMx+OvGVC1wk/KTfh2l4RZRNsfMQ5jNGttUwgs3ZDiubg4DWsrYu3ETCzC7gGdO+f tvJvYV43YEGMsfIBSAXQjB0sH7ncL85O0aVtYZLJqNtdgpt5asn4sOar/BaMAg69Mk PlGQg35UZN6JchM7EMAomGYibgnuSdR3VKZh4UhorTCHm9ZE/GyTjEVd1F0YMt4aS1 KH3yMmcQCMXaA== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1sc2E5-00000000oDm-0Iiu; Thu, 08 Aug 2024 14:26:41 +0200 From: Mauro Carvalho Chehab To: Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , Cleber Rosa , John Snow , linux-kernel@vger.kernel.org, qemu-devel@nongnu.org Subject: [PATCH v6 10/10] scripts/arm_processor_error.py: retrieve mpidr if not filled Date: Thu, 8 Aug 2024 14:26:36 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Add support to retrieve mpidr value via qom-get. Signed-off-by: Mauro Carvalho Chehab --- scripts/arm_processor_error.py | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/scripts/arm_processor_error.py b/scripts/arm_processor_error.py index b464254c8b7c..756935a2263c 100644 --- a/scripts/arm_processor_error.py +++ b/scripts/arm_processor_error.py @@ -5,12 +5,10 @@ # # Copyright (C) 2024 Mauro Carvalho Chehab =20 -# TODO: current implementation has dummy defaults. -# -# For a better implementation, a QMP addition/call is needed to -# retrieve some data for ARM Processor Error injection: -# -# - ARM registers: power_state, mpidr. +# Note: currently it lacks a method to fill the ARM Processor Error CPER +# psci field from emulation. On a real hardware, this is filled only +# when a CPU is not running. Implementing support for it to simulate a +# real hardware is not trivial. =20 import argparse import re @@ -168,11 +166,27 @@ def send_cper(self, args): else: cper["running-state"] =3D 0 =20 + if args.mpidr: + cper["mpidr-el1"] =3D arg["mpidr"] + elif cpus: + get_mpidr =3D { + "execute": "qom-get", + "arguments": { + 'path': cpus[0], + 'property': "x-mpidr" + } + } + ret =3D qmp_cmd.send_cmd(get_mpidr, may_open=3DTrue) + if isinstance(ret, int): + cper["mpidr-el1"] =3D ret + else: + cper["mpidr-el1"] =3D 0 + if arm_valid_init: if args.affinity: cper["valid"] |=3D self.arm_valid_bits["affinity"] =20 - if args.mpidr: + if "mpidr-el1" in cper: cper["valid"] |=3D self.arm_valid_bits["mpidr"] =20 if "running-state" in cper: @@ -360,7 +374,7 @@ def send_cper(self, args): if isinstance(ret, int): arg["midr-el1"] =3D ret =20 - util.data_add(data, arg.get("mpidr-el1", 0), 8) + util.data_add(data, cper["mpidr-el1"], 8) util.data_add(data, arg.get("midr-el1", 0), 8) util.data_add(data, cper["running-state"], 4) util.data_add(data, arg.get("psci-state", 0), 4) --=20 2.45.2