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[173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=PbqB/VGf4r4Gc9nD+4nF5YJ6K6RaL7p0+A+s4fwSp3U=; b=kiVVGP9iHaqnWRdD95CTzNgQ8iLMsUK14AYJAmBADfHZc6pJmNMm/XmoDlvOL0v9C+ qlCJWy/fgnk1DLKjUZXuxaw4pZs0KDc5+llAw3icx/lSm6iTp1aeG23JFwFGDWnCGh90 QnbjMRISXWXLEXD+kGVbZhaL7HwfN9uIt8FFCJBJIh9SvUfze21LjhqwgFqiGH3KJuqZ zRycJB7C8vtWWJdq8FvJ69RQo257rkdFZOtkbxg8YhmUi6oOuETwqpBtSo/aquSPpOIe +xJ6ULaH/9QbT+UCp7/pPRfNYrMYCdhFJqSNqU+5nQa6FAl4ieMmgOiIIDD1J3wACEcO nxVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=PbqB/VGf4r4Gc9nD+4nF5YJ6K6RaL7p0+A+s4fwSp3U=; b=CKuvhdSFln4R4eOA6niN1dHiAqM+qRtqqNo4jctFy4sEEs5h81gDjIhHkzP/jv7h1T I0OJtT90MPCe7+ZvoCFUnvw0KYutQe8eYrE4QIKKG6lKyrfDcVDzF+JKKJX6hollzS6b VYpmaWLlKGf42OepT7gHfbcNfUCfmvN6v7jJ1iIRjhoeQxKRo5BZN2rhEKHX2BsJcvjC wz/ahhih+AzQocez9nMZhRCLlzXyxF9b+aPOd3g7BU0ow+BTop5aIaehgoa1txfnxMH1 Iy1YJ/yp3N9yr3qVIPQViClgfrit83U9CFHe+TeAa56SjCD2ruXfFMbZ2Kath1Ugaa9e 1Qvg== X-Gm-Message-State: AJaThX4dKQEf9IjjV/goS2a5ha8wmI9xbfhB+LiD1aqNYWb4zZLed22P GP8XEPtQvfQJT1BF95c/CChWzA== X-Google-Smtp-Source: AGs4zMZz/WXSU8ju8O4lyxTCFJtZoXi+3/NFkY8u8fSpYR6PscZS6jHkFZ20blMR6V1aNJasAQ3KlA== X-Received: by 10.36.101.140 with SMTP id u134mr11534606itb.108.1511733594189; Sun, 26 Nov 2017 13:59:54 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:09 -0600 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH 11/17] e500: derive baud from CCB clock X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The CCB (Complex Core Bus) clock is the reference for the DUARTs with an extra divide by 16. From the mpc8540, mpc8544, and P2010 ref manuals. CCB=3D333MHz, with divider=3D0x87a gives ~9600 baud. 333e6 Hz/(16*0x87a) =3D 9591 Hz. This is verified with a real mpc8540. The existing value for the mpc8544ds boards is replaced. Previously the uart "clock-frequency" device tree node was left as zero, and at some point either u-boot or Linux picks a value inconsistent with the frequency given to serial_mm_init(). The FIFO timeout calculated from this was incorrect. Now use an arbitrary (valid) CCB frequency of 333MHz in the device tree and for the UART. Signed-off-by: Michael Davidsaver --- hw/ppc/e500.c | 9 ++++++++- hw/ppc/e500_ccsr.c | 16 ++++++++++++---- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 2d87d91582..cfd5ed0152 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -49,6 +49,12 @@ =20 #define RAM_SIZES_ALIGN (64UL << 20) =20 +/* Somewhat arbitrarily choosen Complex Core Bus frequency + * for our simulation (real freq of mpc8544ds board unknown) + * Used in baud rate calculations. + */ +#define CCB_FREQ (333333333) + /* TODO: parameterize * Some CCSR offsets duplicated in e500_ccsr.c */ @@ -113,7 +119,7 @@ static void dt_serial_create(void *fdt, unsigned long l= ong offset, qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); - qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); + qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", CCB_FREQ); qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); @@ -759,6 +765,7 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) dev =3D qdev_create(NULL, "e500-ccsr"); object_property_add_child(qdev_get_machine(), "e500-ccsr", OBJECT(dev), NULL); + qdev_prop_set_uint32(dev, "ccb-freq", CCB_FREQ); qdev_prop_set_uint32(dev, "mpic-model", params->mpic_version); qdev_prop_set_uint32(dev, "base", params->ccsrbar_base); qdev_prop_set_uint32(dev, "ram-size", ram_size); diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index f1adba4e54..c479ed91ee 100644 --- a/hw/ppc/e500_ccsr.c +++ b/hw/ppc/e500_ccsr.c @@ -69,6 +69,7 @@ typedef struct { uint32_t merrd; =20 uint32_t porpllsr; + uint32_t ccb_freq; =20 DeviceState *pic; } CCSRState; @@ -272,15 +273,21 @@ static void e500_ccsr_realize(DeviceState *dev, Error= **errp) /* Note: MPIC internal interrupts are offset by 16 */ =20 /* DUARTS */ + /* for mpc8540, mpc8544, and P2010 (unmodeled), the DUART reference cl= ock + * is the CCB clock divided by 16. + * So baud rate is CCB/(16*divider) + */ if (serial_hds[0]) { - serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(0), - 0, qdev_get_gpio_in(ccsr->pic, 16 + 26), 399193, + serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(0), 0, + qdev_get_gpio_in(ccsr->pic, 16 + 26), + ccsr->ccb_freq / 16u, serial_hds[0], DEVICE_BIG_ENDIAN); } =20 if (serial_hds[1]) { - serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(1), - 0, qdev_get_gpio_in(ccsr->pic, 16 + 26), 399193, + serial_mm_init(&ccsr->iomem, E500_DUART_OFFSET(1), 0, + qdev_get_gpio_in(ccsr->pic, 16 + 26), + ccsr->ccb_freq / 16u, serial_hds[1], DEVICE_BIG_ENDIAN); } =20 @@ -290,6 +297,7 @@ static Property e500_ccsr_props[] =3D { DEFINE_PROP_UINT32("base", CCSRState, defbase, 0xff700000), DEFINE_PROP_UINT32("ram-size", CCSRState, ram_size, 0), DEFINE_PROP_UINT32("porpllsr", CCSRState, porpllsr, 0), + DEFINE_PROP_UINT32("ccb-freq", CCSRState, ccb_freq, 333333333u), /* "mpic-model" aliased from MPIC */ DEFINE_PROP_END_OF_LIST() }; --=20 2.11.0