From nobody Wed Nov 27 14:34:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169857770109957.85084730752078; Sun, 29 Oct 2023 04:08:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qx3dq-0007Vy-R9; Sun, 29 Oct 2023 07:07:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qx3do-0007Oa-Sj for qemu-devel@nongnu.org; Sun, 29 Oct 2023 07:07:36 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qx3dk-0000Hu-Nd for qemu-devel@nongnu.org; Sun, 29 Oct 2023 07:07:36 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 24AA4756082; Sun, 29 Oct 2023 12:07:33 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id F0B1C7560A3; Sun, 29 Oct 2023 12:07:32 +0100 (CET) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 1/4] hw/isa/vt82c686: Bring back via_isa_set_irq() To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Jiaxun Yang , Bernhard Beschow , vr_qemu@t-online.de Date: Sun, 29 Oct 2023 12:07:32 +0100 (CET) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1698577704105100005 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The VIA intergrated south bridge chips combine several functions and allow routing their interrupts to any of the ISA IRQs (also allowing multiple components to share the same ISA IRQ, e.g. pegasos2 firmware configures USB, sound and PCI to all use IRQ 9). Bring back via_isa_set_irq() and change it to take the PCIDevice that wants to change an IRQ and keep track of the interrupt status of each source separately and do the mapping to ISA IRQ within the ISA bridge to allow different sources to control the same ISA IRQ lines. This may not handle cases when the ISA IRQ is also controlled by devices directly, not going through via_isa_set_irq() such as serial, parallel or keyboard but these IRQs being conventionally fixed are not likely for guests to change or share with other devices so hopefully this does not cause a problem in practice. This reverts commit 4e5a20b6da9b1f6d2e9621ed7eb8b239560104ae. Signed-off-by: BALATON Zoltan --- hw/isa/vt82c686.c | 39 +++++++++++++++++++++++++++++++++++++++ include/hw/isa/vt82c686.h | 2 ++ 2 files changed, 41 insertions(+) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 57bdfb4e78..c1826c77eb 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -549,6 +549,7 @@ struct ViaISAState { PCIDevice dev; qemu_irq cpu_intr; qemu_irq *isa_irqs_in; + uint16_t isa_irq_state[ISA_NUM_IRQS]; ViaSuperIOState via_sio; MC146818RtcState rtc; PCIIDEState ide; @@ -592,6 +593,44 @@ static const TypeInfo via_isa_info =3D { }, }; =20 +void via_isa_set_irq(PCIDevice *d, int pin, int level) +{ + ViaISAState *s =3D VIA_ISA(pci_get_function_0(d)); + int n =3D PCI_FUNC(d->devfn); + uint8_t isa_irq =3D d->config[PCI_INTERRUPT_LINE], max_irq =3D 15; + + switch (n) { + case 2: /* USB ports 0-1 */ + case 3: /* USB ports 2-3 */ + max_irq =3D 14; + break; + } + + if (unlikely(isa_irq > max_irq || isa_irq =3D=3D 2)) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing %d for %d", + isa_irq, n); + return; + } + if (isa_irq =3D=3D 0) { + return; /* disabled */ + } + + /* + * In addition to recording status of sources mapped to each isa_irq we + * keep track of all sources in IRQ 0 and use that as a mask to avoid = stuck + * interrupts in case mapping of a source is changed while IRQ is rais= ed. + */ + if (level) { + s->isa_irq_state[isa_irq] |=3D BIT(n); + s->isa_irq_state[0] |=3D BIT(n); + } else { + s->isa_irq_state[isa_irq] &=3D ~BIT(n); + s->isa_irq_state[0] &=3D ~BIT(n); + } + s->isa_irq_state[isa_irq] &=3D s->isa_irq_state[0]; + qemu_set_irq(s->isa_irqs_in[isa_irq], !!s->isa_irq_state[isa_irq]); +} + static void via_isa_request_i8259_irq(void *opaque, int irq, int level) { ViaISAState *s =3D opaque; diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index b6e95b2851..da1722daf2 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -34,4 +34,6 @@ struct ViaAC97State { uint32_t ac97_cmd; }; =20 +void via_isa_set_irq(PCIDevice *d, int n, int level); + #endif --=20 2.30.9