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bh=uG+2YaSHQU6xVjUZFZRIGwj39Oo0ZuoiehAmF5ZQwZg=; b=Q6MKACx/8UDVyEasXkU9JsvsS+hEvFkVxUvxewF2jNgWzdC/mb4oFaXi KKXwYn1C776ddeBHFvlnpQYpvmL4aave0WLTkynone+Kkzahm37wU/u/I qq/1LeOT+qjB54bVInzfpxdwhJhsX3JCZcHmXvobHjQMw/JweClED/mzF z+WKm+Sw7h+nj7hxBHHdGy8yqDv04TxPJrU3e/Y4yUoSb2L0cBZ0DIw2H gxFs8iftJajUWjNSC4/1zzwEtRZ3nrfgKGnPw0RZxhfcP758+tSG216Ig dXp6tFwfYY8545AlYaaanXMytZF77Qydi9M+JHb3D/q6Rj4CfLuFley1A A==; IronPort-SDR: s/0XeVtlf4BMgn8Z3qGJ+DB9ItsfGNtID6XCClOqdBLXpnbIT8Ym3HNp5JSvUk687jPNeT8pVB y3XR5dFOQ6ZAojzrOKj7w7oklwssd8Q6FirgZI/bcYl6ocSDoAwQHi6h380RocxUkwWpZfhA5M 30N/86TM1lTaiRlNh9iUw+mj6wmUNWqXn+GrJOwuW6gV+JgbLM2qXhXNu6B4z6ijPbwyxuJWI0 l4S1u/ODKB6vpywrd4aOQew7+8HcIkXMyW7423LCAU0IEdKgG4v2zRkCAR9Q7eh87N7R9wh1AL hGQ= X-IronPort-AV: E=Sophos;i="5.64,307,1559491200"; d="scan'208";a="220533152" IronPort-SDR: 6y2TJXBsXJqiEW7H0IRlq8Gskl5uch3EpqHnUox44uUXpuVjrMcgiSo/3M1oPeT9Yil5S4bXPH BR6IiuYvPTlyUtF2UuA/refABNY3h8vII2A07FOAd8tkz3SnkDzEkZoiJuAUO3gSbba2ElOej7 8gMKZAEenOh9WhkaTFLuMT3HhVY6Zi2uhdC6iVp8cNgi/GqRyuPqqinMrrQ5DaO/HFW/RhhJa/ qnG5l2CpicYwZSOATvE/zJ6c/Az/0PYd/ACH+uvuMnMhIrz903S9nhkZ770yR7PFrTE6YTLh+Y 94/EicYVH3pYdkyKZwlhBoXt IronPort-SDR: Qs4z0ii4JlUtoiuWAbDhT2dVcrzxC5KgxljZIBBHzsShmFcMNR1Svufr2yzwVE/wTPPlnV7NDb nyDLk5KKSUow65YgIdu0VAIOI9wRR3nhJ15ES7eLLAEs/LCK/rfaFUfX6oXCw9bG/T23XBucR3 WeEx4O6M+WgHVgdCvYZBVhbarjTLVIh38Pl/WQg+XGCf7wRQv2QZbd6/1EsUuDol67anLs06/S I8cDhV/dU3XA0+0+2+HbXN8VhZnyN/rBF+50LyYIJBSLER6unQgd1WoEEGji7vwN1Vu8jGDrHP Qpc= From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 25 Jul 2019 11:52:09 -0700 Message-Id: X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH-4.2 v1 4/6] target/riscv: Create function to test if FP is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Let's creaate a function that tests if floating point support is enabled. We can then protect all floating point operations based on if they are enabled. This patch so far doesn't change anything, it's just preparing for the Hypervisor support for floating point operations. Signed-off-by: Alistair Francis Reviewed-by: Christophe de Dinechin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 6 +++++- target/riscv/cpu_helper.c | 10 ++++++++++ target/riscv/csr.c | 19 ++++++++++--------- 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0adb307f32..2dc9b17678 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -255,6 +255,7 @@ void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); +bool riscv_cpu_fp_enabled(CPURISCVState *env); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, @@ -298,7 +299,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *flags =3D TB_FLAGS_MSTATUS_FS; #else - *flags =3D cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); + *flags =3D cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + *flags |=3D env->mstatus & MSTATUS_FS; + } #endif } =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f027be7f16..225e407cff 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,6 +71,16 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 #if !defined(CONFIG_USER_ONLY) =20 +/* Return true is floating point support is currently enabled */ +bool riscv_cpu_fp_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_FS) { + return true; + } + + return false; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index af3b762c8b..7b73b73cf7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *o= ps) static int fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -108,7 +108,7 @@ static int pmp(CPURISCVState *env, int csrno) static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -119,7 +119,7 @@ static int read_fflags(CPURISCVState *env, int csrno, t= arget_ulong *val) static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |=3D MSTATUS_FS; @@ -131,7 +131,7 @@ static int write_fflags(CPURISCVState *env, int csrno, = target_ulong val) static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -142,7 +142,7 @@ static int read_frm(CPURISCVState *env, int csrno, targ= et_ulong *val) static int write_frm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |=3D MSTATUS_FS; @@ -154,7 +154,7 @@ static int write_frm(CPURISCVState *env, int csrno, tar= get_ulong val) static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -166,7 +166,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, tar= get_ulong *val) static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |=3D MSTATUS_FS; @@ -307,6 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) { target_ulong mstatus =3D env->mstatus; target_ulong mask =3D 0; + int dirty; =20 /* flush tlb on mstatus fields that affect VM */ if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { @@ -340,8 +341,8 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 - int dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | - ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); + dirty =3D riscv_cpu_fp_enabled(env) | + ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); env->mstatus =3D mstatus; =20 --=20 2.22.0