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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Bernhard Beschow , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 59/83] hw/isa/piix4: Rename reset control operations to match PIIX3 Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697644824541100007 From: Bernhard Beschow Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Michael S. Tsirkin Message-Id: <20231007123843.127151-18-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin --- hw/isa/piix4.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 9c8b6c98ab..eb456622c5 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -148,8 +148,8 @@ static void piix4_request_i8259_irq(void *opaque, int i= rq, int level) qemu_set_irq(s->cpu_intr, level); } =20 -static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int len) +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) { PIIX4State *s =3D opaque; =20 @@ -161,16 +161,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr= , uint64_t val, s->rcr =3D val & 2; /* keep System Reset type only */ } =20 -static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) { PIIX4State *s =3D opaque; =20 return s->rcr; } =20 -static const MemoryRegionOps piix4_rcr_ops =3D { - .read =3D piix4_rcr_read, - .write =3D piix4_rcr_write, +static const MemoryRegionOps rcr_ops =3D { + .read =3D rcr_read, + .write =3D rcr_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -194,7 +194,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, "intr", 1); =20 - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); --=20 MST