From nobody Mon Feb 9 16:12:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1613026689; cv=none; d=zohomail.com; s=zohoarc; b=Kt23BWTR1mNbOawKjD+o2avK+RFeO+q7MbKnk1V7ov5xOfkj3QFt2U8CSOAHctxJosD4Qv9/2FX7cNzPAmekWebiTYoH2AlqaAQezX8AnT+pkrtqlehTpHWMtTScn0eJQOaBU8bX3/AtsBI4t3HLbG0QEdFCKDL5g3K2ZfuOSO0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613026689; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=cPfV3QAjwKZ80+hoOut2Cx4S+BHtUBjozxlDJpF6uWM=; b=Qx45gdCGwK0XvvvtjdjKfN6SNkwlKwdRFohx/lnOBvbfiidF0ORPJcD0bS/i6ak5nuzY6cZIBH6NU6DiOCjRcn8no5bFM1/Os7NE6K9D3hWdlULIUtlmhNfDLOmnsAwqpWAsr57GqM15/VYhBs3AOHY5YdBWOUWhDbwLEfgJ7Y8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613026689248768.6317919675704; Wed, 10 Feb 2021 22:58:09 -0800 (PST) Received: from localhost ([::1]:33080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lA5vU-00082Z-70 for importer@patchew.org; Thu, 11 Feb 2021 01:58:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lA5mQ-0002Bi-5N for qemu-devel@nongnu.org; Thu, 11 Feb 2021 01:48:46 -0500 Received: from mga11.intel.com ([192.55.52.93]:48349) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lA5mK-00085A-FL for qemu-devel@nongnu.org; Thu, 11 Feb 2021 01:48:45 -0500 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2021 22:48:24 -0800 Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2021 22:48:24 -0800 IronPort-SDR: 1NmmyQTYFVEUqBnkc8DFPrOkgQNjf04aKH2xZQtd/U7m0D8DemymXFOAp6ngvOmyNIsP46fXx/ er4q8UaiHqdg== X-IronPort-AV: E=McAfee;i="6000,8403,9891"; a="178692964" X-IronPort-AV: E=Sophos;i="5.81,169,1610438400"; d="scan'208";a="178692964" IronPort-SDR: C19OSWzX1fuVKdC/y2kXbi4FpIoh19xHonMRpvaUHLO/TUXdo2ppf3hkFd2j1SJ4kqhriKHuK4 Ru5KTxgEybUw== X-IronPort-AV: E=Sophos;i="5.81,169,1610438400"; d="scan'208";a="588716280" From: Isaku Yamahata To: qemu-devel@nongnu.org, imammedo@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com Subject: [PATCH v3 07/10] hw/i386: declare ACPI mother board resource for MMCONFIG region Date: Wed, 10 Feb 2021 22:46:43 -0800 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.93; envelope-from=isaku.yamahata@intel.com; helo=mga11.intel.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Declare PNP0C01 device to reserve MMCONFIG region to conform to the spec better and play nice with guest BIOSes/OSes. According to PCI Firmware Specification[0], MMCONFIG region must be reserved by declaring a motherboard resource. It's optional to reserve the region in memory map by Int 15 E820h or EFIGetMemoryMap. Guest Linux checks if the MMCFG region is reserved by bios memory map or ACPI resource. If it's not reserved, Linux falls back to legacy PCI configuration access. TDVF [1] [2] doesn't reserve MMCONFIG the region in memory map. On the other hand OVMF reserves it in memory map without declaring a motherboard resource. With memory map reservation, linux guest uses MMCONFIG region. However it doesn't comply to PCI Firmware specification. [0] PCI Firmware specification Revision 3.2 4.1.2 MCFG Table Description table 4-2 NOTE 2 If the operating system does not natively comprehend reserving the MMCFG region, The MMCFG region must e reserved by firmware. ... For most systems, the mortheroard resource would appear at the root of the ACPI namespace (under \_SB)... The resource can optionally be returned in Int15 E820h or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource [1] TDX: Intel Trust Domain Extension https://software.intel.com/content/www/us/en/develop/articles/intel-tru= st-domain-extensions.html [2] TDX Virtual Firmware https://github.com/tianocore/edk2-staging/tree/TDVF The change to DSDT is as follows. @@ -68,32 +68,51 @@ If ((CDW3 !=3D Local0)) { CDW1 |=3D 0x10 } CDW3 =3D Local0 } Else { CDW1 |=3D 0x04 } Return (Arg3) } } + + Device (DRAC) + { + Name (_HID, "PNP0C01" /* System Board */) // _HID: Hardware ID + Name (RBUF, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFix= ed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x00000000B0000000, // Range Minimum + 0x00000000BFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin= gs + { + Return (RBUF) /* \_SB_.DRAC.RBUF */ + } + } } Scope (_SB) { Device (HPET) { Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _H= ID: Hardware ID Name (_UID, Zero) // _UID: Unique ID OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) Field (HPTM, DWordAcc, Lock, Preserve) { VEND, 32, PRD, 32 } Method (_STA, 0, NotSerialized) // _STA: Status Signed-off-by: Isaku Yamahata --- hw/i386/acpi-build.c | 46 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 00cc119362..e369908b1a 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1072,6 +1072,46 @@ static void build_q35_pci0_int(Aml *table) aml_append(table, sb_scope); } =20 +static Aml *build_q35_dram_controller(void) +{ + AcpiMcfgInfo mcfg; + Aml *dev; + Aml *rbuf; + Aml *resource_template; + Aml *rbuf_name; + Aml *crs; + + if (!acpi_get_mcfg(&mcfg)) { + return NULL; + } + + /* DRAM controller */ + dev =3D aml_device("DRAC"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); + + resource_template =3D aml_resource_template(); + aml_append(resource_template, + aml_qword_memory(AML_POS_DECODE, + AML_MIN_FIXED, + AML_MAX_FIXED, + AML_NON_CACHEABLE, + AML_READ_WRITE, + 0x0000000000000000, + mcfg.base, + mcfg.base + mcfg.size - 1, + 0x0000000000000000, + mcfg.size)); + rbuf =3D aml_name_decl("RBUF", resource_template); + aml_append(dev, rbuf); + + crs =3D aml_method("_CRS", 0, AML_SERIALIZED); + rbuf_name =3D aml_name("RBUF"); + aml_append(crs, aml_return(rbuf_name)); + aml_append(dev, crs); + + return dev; +} + static void build_q35_isa_bridge(Aml *table) { Aml *dev; @@ -1212,7 +1252,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Range *pci_hole, Range *pci_hole64, MachineState *machine) { CrsRangeEntry *entry; - Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; + Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs, *drac; CrsRangeSet crs_range_set; PCMachineState *pcms =3D PC_MACHINE(machine); PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(machine); @@ -1256,6 +1296,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_UID", aml_int(0))); aml_append(dev, build_q35_osc_method()); aml_append(sb_scope, dev); + drac =3D build_q35_dram_controller(); + if (drac) { + aml_append(sb_scope, drac); + } =20 if (pm->smi_on_cpuhp) { /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ --=20 2.17.1