From nobody Tue Nov 26 19:47:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705615396838546.4565238891391; Thu, 18 Jan 2024 14:03:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQaSW-00074f-MX; Thu, 18 Jan 2024 17:02:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQaSQ-0006yH-I7; Thu, 18 Jan 2024 17:01:54 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQaSM-000535-EP; Thu, 18 Jan 2024 17:01:54 -0500 Received: from zero.eik.bme.hu (localhost [127.0.0.1]) by zero.eik.bme.hu (Postfix) with ESMTP id 7D51C4E610F; Thu, 18 Jan 2024 23:01:46 +0100 (CET) Received: from zero.eik.bme.hu ([127.0.0.1]) by zero.eik.bme.hu (zero.eik.bme.hu [127.0.0.1]) (amavisd-new, port 10028) with ESMTP id eyLQ3xcRNpLj; Thu, 18 Jan 2024 23:01:44 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 7A0E54E60FB; Thu, 18 Jan 2024 23:01:44 +0100 (CET) X-Virus-Scanned: amavisd-new at eik.bme.hu Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v5 2/9] target/ppc: Readability improvements in exception handlers MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , clg@kaod.org Date: Thu, 18 Jan 2024 23:01:44 +0100 (CET) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1705615397242100001 Content-Type: text/plain; charset="utf-8" Improve readability by shortening some long comments, removing comments that state the obvious and dropping some empty lines so they don't distract when reading the code. Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin --- target/ppc/cpu.h | 1 + target/ppc/excp_helper.c | 179 +++++++-------------------------------- 2 files changed, 33 insertions(+), 147 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..2f9b610abc 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2902,6 +2902,7 @@ static inline bool ppc_has_spr(PowerPCCPU *cpu, int s= pr) } =20 #if !defined(CONFIG_USER_ONLY) +/* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) { PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b8fd01d04c..39eefc168a 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -403,9 +403,8 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, tar= get_ulong vector, * We don't use hreg_store_msr here as already have treated any * special case that could occur. Just store MSR and update hflags * - * Note: We *MUST* not use hreg_store_msr() as-is anyway because it - * will prevent setting of the HV bit which some exceptions might need - * to do. + * Note: We *MUST* not use hreg_store_msr() as-is anyway because it wi= ll + * prevent setting of the HV bit which some exceptions might need to d= o. */ env->nip =3D vector; env->msr =3D msr; @@ -447,25 +446,15 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int exc= p) { CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1; + int srr0 =3D SPR_SRR0, srr1 =3D SPR_SRR1; =20 /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 - /* - * new interrupt handler msr preserves existing ME unless - * explicitly overridden. - */ + /* new interrupt handler msr preserves ME unless explicitly overriden = */ new_msr =3D env->msr & (((target_ulong)1 << MSR_ME)); =20 - /* target registers */ - srr0 =3D SPR_SRR0; - srr1 =3D SPR_SRR1; - - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -475,7 +464,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -487,7 +475,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); - srr0 =3D SPR_40x_SRR2; srr1 =3D SPR_40x_SRR3; break; @@ -558,12 +545,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) break; } =20 - /* Save PC */ env->spr[srr0] =3D env->nip; - - /* Save MSR */ env->spr[srr1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -575,16 +558,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int exc= p) /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 - /* - * new interrupt handler msr preserves existing ME unless - * explicitly overridden - */ + /* new interrupt handler msr preserves ME unless explicitly overriden = */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -594,7 +571,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -604,7 +580,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); - break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); @@ -632,11 +607,9 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; break; @@ -712,20 +685,11 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int exc= p) break; } =20 - /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... - */ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { new_msr |=3D (target_ulong)1 << MSR_LE; } - - /* Save PC */ env->spr[SPR_SRR0] =3D env->nip; - - /* Save MSR */ env->spr[SPR_SRR1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -737,16 +701,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int exc= p) /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 - /* - * new interrupt handler msr preserves existing ME unless - * explicitly overridden - */ + /* new interrupt handler msr preserves ME unless explicitly overriden = */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -756,7 +714,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -764,7 +721,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); - break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); @@ -792,11 +748,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; break; @@ -865,12 +819,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int exc= p) case POWERPC_EXCP_DLTLB: /* Data load TLB miss = */ case POWERPC_EXCP_DSTLB: /* Data store TLB miss = */ ppc_excp_debug_sw_tlb(env, excp); - msr |=3D env->crf[0] << 28; msr |=3D env->error_code; /* key, D/I, S/L bits */ /* Set way using a LRU mechanism */ msr |=3D ((env->last_way + 1) & (env->nb_ways - 1)) << 17; - break; case POWERPC_EXCP_IABR: /* Instruction address breakpoint = */ case POWERPC_EXCP_SMI: /* System management interrupt = */ @@ -885,20 +837,11 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int exc= p) break; } =20 - /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... - */ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { new_msr |=3D (target_ulong)1 << MSR_LE; } - - /* Save PC */ env->spr[SPR_SRR0] =3D env->nip; - - /* Save MSR */ env->spr[SPR_SRR1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -910,16 +853,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int ex= cp) /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 - /* - * new interrupt handler msr preserves existing ME unless - * explicitly overridden - */ + /* new interrupt handler msr preserves ME unless explicitly overriden = */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -929,7 +866,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -937,7 +873,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) powerpc_mcheck_checkstop(env); /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); - break; case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); @@ -965,11 +900,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int exc= p) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; break; @@ -1050,20 +983,11 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int e= xcp) break; } =20 - /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... - */ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { new_msr |=3D (target_ulong)1 << MSR_LE; } - - /* Save PC */ env->spr[SPR_SRR0] =3D env->nip; - - /* Save MSR */ env->spr[SPR_SRR1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -1071,24 +995,18 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int = excp) { CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1; - - msr =3D env->msr; + int srr0 =3D SPR_SRR0, srr1 =3D SPR_SRR1; =20 /* - * new interrupt handler msr preserves existing ME unless - * explicitly overridden + * Book E does not play games with certain bits of xSRR1 being MSR save + * bits and others being error status. xSRR1 is the old MSR, period. */ - new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); + msr =3D env->msr; =20 - /* target registers */ - srr0 =3D SPR_SRR0; - srr1 =3D SPR_SRR1; + /* new interrupt handler msr preserves ME unless explicitly overriden = */ + new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 - /* - * Hypervisor emulation assistance interrupt only exists on server - * arch 2.05 server or later. - */ + /* HV emu assistance interrupt only exists on server arch 2.05 or late= r */ if (excp =3D=3D POWERPC_EXCP_HV_EMU) { excp =3D POWERPC_EXCP_PROGRAM; } @@ -1108,7 +1026,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int e= xcp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 switch (excp) { @@ -1152,11 +1069,9 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int = excp) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; env->spr[SPR_BOOKE_ESR] =3D ESR_FP; @@ -1257,12 +1172,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int = excp) } #endif =20 - /* Save PC */ env->spr[srr0] =3D env->nip; - - /* Save MSR */ env->spr[srr1] =3D msr; - powerpc_set_excp_state(cpu, vector, new_msr); } =20 @@ -1375,21 +1286,17 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) { CPUPPCState *env =3D &cpu->env; target_ulong msr, new_msr, vector; - int srr0, srr1, lev =3D -1; + int srr0 =3D SPR_SRR0, srr1 =3D SPR_SRR1, lev =3D -1; =20 /* new srr1 value excluding must-be-zero bits */ msr =3D env->msr & ~0x783f0000ULL; =20 /* - * new interrupt handler msr preserves existing HV and ME unless - * explicitly overridden + * new interrupt handler msr preserves HV and ME unless explicitly + * overriden */ new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); =20 - /* target registers */ - srr0 =3D SPR_SRR0; - srr1 =3D SPR_SRR1; - /* * check for special resume at 0x100 from doze/nap/sleep/winkle on * P7/P8/P9 @@ -1414,7 +1321,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) cpu_abort(env_cpu(env), "Raised an exception without defined vector %d\n", excp); } - vector |=3D env->excp_prefix; =20 if (is_prefix_insn_excp(cpu, excp)) { @@ -1431,7 +1337,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) */ new_msr |=3D (target_ulong)MSR_HVB; } - /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 @@ -1449,23 +1354,17 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) { bool lpes0; =20 - /* - * LPES0 is only taken into consideration if we support HV - * mode for this CPU. - */ + /* LPES0 is only taken into consideration if we support HV mode */ if (!env->has_hv_mode) { break; } - lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); - if (!lpes0) { new_msr |=3D (target_ulong)MSR_HVB; new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); srr0 =3D SPR_HSRR0; srr1 =3D SPR_HSRR1; } - break; } case POWERPC_EXCP_ALIGN: /* Alignment exception = */ @@ -1488,11 +1387,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int = excp) powerpc_reset_excp_state(cpu); return; } - /* - * FP exceptions always have NIP pointing to the faulting - * instruction, so always use store_next and claim we are - * precise in the MSR. + * NIP always points to the faulting instruction for FP except= ions, + * so always use store_next and claim we are precise in the MS= R. */ msr |=3D 0x00100000; break; @@ -1656,21 +1553,13 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) break; } =20 - /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... - */ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { new_msr |=3D (target_ulong)1 << MSR_LE; } - new_msr |=3D (target_ulong)1 << MSR_SF; =20 if (excp !=3D POWERPC_EXCP_SYSCALL_VECTORED) { - /* Save PC */ env->spr[srr0] =3D env->nip; - - /* Save MSR */ env->spr[srr1] =3D msr; } =20 @@ -1679,19 +1568,15 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); /* Deliver interrupt to L1 by returning from the H_ENTER_NESTED ca= ll */ vhc->deliver_hv_excp(cpu, excp); - powerpc_reset_excp_state(cpu); - } else { /* Sanity check */ if (!(env->msr_mask & MSR_HVB) && srr0 =3D=3D SPR_HSRR0) { cpu_abort(env_cpu(env), "Trying to deliver HV exception (HSRR)= %d " "with no HV support\n", excp); } - /* This can update new_msr and vector if AIL applies */ ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector); - powerpc_set_excp_state(cpu, vector, new_msr); } } --=20 2.30.9