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x=1614821789; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RZGMEj8rnsYsgj6Tk32enNLXX4pUHrwlRy91vxUcAFs=; b=eHHTBxC228ZNnaDMHOBhLBCE7pZaB8DDmyrRoH1VtDwIX58EP/0ekhSm G6Dg7DgqJSTtDNM4EL91UrQESLbjNzMmq2yOPShGhRPxioIgoS/+Ocf4E xi6hQ1Uz7/SAUrN4weYfsCdGe4w7jJh/CK3wl3Sh2e9Rx+Z4CDRQzhxbo 5iFUVA6J9OzWqxUZ0SRgxmbb0h7ZoTR+/D+tnCA6z3w3hkx2fXL8Cgl4L NQ+uWjFw+1XRtOjTIX9C4mtZ76SCVq+bSLCeLITFVzPqBZBtUuHcN7Yn+ G8MtXDc83XZ3BcAFS7MpSz5MDcTQq8b4qY7uquP2uCItUzEpWz/AFS5Zg g==; IronPort-SDR: UxCGwN7B8zlSZ4cpLNVPXQFsVHZeYEdSr5xrBsSLcNqM2ybk4pdUMLIEdQwqpvpkWOEph4gtEy Cau6hcVSUtm/MCseMYLlFsCJB53W53te2TFlZ3iZh85oG7y9dJW2p1TxA2TOSL4bDGOWPzE/Hy nsLrs0gci27pKNxXb7SYSkYAJmd9fUymuk02duC3nHYYREDB0oOzie3RkvuiTA6+P1ol9Q7+XQ mYBfpBuh9WHdQD4H+9WddhIpQPvqfgFeAMN2wD7/fM+s/A5Cdnsop4PpuEGPmNXcfuMSQ+bHDS F/0= X-IronPort-AV: E=Sophos;i="5.70,511,1574092800"; d="scan'208";a="131866061" IronPort-SDR: sOl+Bhyb4NFVap+qtqa3MaodzFHKbdv3TzGKq7SRRr+Glvq1Eg9rwO3kQkL9yPP8p6AKsqpAfo yXo7UUDBgKjGrqPCam4b3n1YqfwAgs+2e43MRQ/aCCtl6hGbynAG72suBFvXqUuIBCXB/1byAb ON4Gx0+uH0h6BWHcGhBqYSNE/KapC4cIWBvySaVx4kp5a9XAk5j0Q5HjA98+BE+bqRh4A7pLZ7 nzJuFQ09Z8BDViuwkjQJIdHsyoNyTIOi/Nog49pQTQ4OK0WOkM5X6dyQeFY9YaeLGjat+xbGpY Ee2oRZlUdOY+xLlsV/inCSmQ IronPort-SDR: 2j8N8RQsraNEVUYYYc9XRnf46+7QO4N73zwN3MultxmD0Y1gsL9Zjungj4vk+2sVK3YUHu5+Fk 0070HmnJHxnFsuR+mmTDzZnqomW0fgqGqjdQ+wCLVrfRZDMXPNkfl0E2iWyYiHPa1T1CpJmRsV SjrGi8mtINsMzx6vrfMG3C/8ypnL29+/cdKL/vnySBbjhoEHibi0S2JpE+U2o9RTKZURt8CQ4+ 5chBLeVFo5bw+A/TGWz+Q8bosi4JUG+ojnKJW/yoZhtnO893cQRCgMVcKqoiqapo/OEtjfkvPz oE4= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC Date: Tue, 3 Mar 2020 17:29:13 -0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.153.144 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to the sifive_u SoC to specify the board serial number. When not given, the default serial number 1 is used. Suggested-by: Bin Meng Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 8 +++++++- include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9a0145b5b4..e52f9d0bd4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -488,7 +488,7 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_SIFIVE_U_PRCI); sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), TYPE_SIFIVE_U_OTP); - qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL); + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), TYPE_CADENCE_GEM); } @@ -607,10 +607,16 @@ static void riscv_sifive_u_soc_realize(DeviceState *d= ev, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } =20 +static Property riscv_sifive_u_soc_props[] =3D { + DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), + DEFINE_PROP_END_OF_LIST() +}; + static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); =20 + device_class_set_props(dc, riscv_sifive_u_soc_props); dc->realize =3D riscv_sifive_u_soc_realize; /* Reason: Uses serial_hds in realize function, thus can't be used twi= ce */ dc->user_creatable =3D false; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 82667b5746..a2baa1de5f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState { SiFiveUPRCIState prci; SiFiveUOTPState otp; CadenceGEMState gem; + + uint32_t serial; } SiFiveUSoCState; =20 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") --=20 2.25.1