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Mon, 19 May 2025 17:20:23 +0200 (CEST) Received: (qmail 1422 invoked by uid 990); 19 May 2025 15:20:23 -0000 Received: from unknown (HELO unkown) (::1) by skiff.uberspace.de (Haraka/3.0.1) with ESMTPSA; Mon, 19 May 2025 17:20:23 +0200 Authentication-Results: skiff.uberspace.de; auth=pass (plain) From: Julian Ganz To: qemu-devel@nongnu.org Cc: Julian Ganz , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v5 06/25] target/arm: call plugin trap callbacks Date: Mon, 19 May 2025 17:19:46 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Bar: ----- X-Rspamd-Report: REPLY(-4) BAYES_HAM(-2.999635) MID_CONTAINS_FROM(1) MIME_GOOD(-0.1) R_MISSING_CHARSET(0.5) X-Rspamd-Score: -5.599635 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nut.email; s=uberspace; h=from:to:cc:subject:date; bh=6EPHJrxC3MYFqp3FW+kc56Uyv/wE7rHT4/YdFGMzvNc=; b=SDHW1W4XgHTidjjC4jAYj6gMV5VckHVrtoMWVn9aGgoSi0KxYUcoQbZ2KBDPbHIbOhvTaxcZr3 odEIJYwpZ4nCLJQ0SqPeUlOJLdSYkVk1Yl+uv/86V8R4uuV/Rqul/yXXRPhoQ5ag+HNELC4jARZM aqHHRZTcC5PBEmVWhf+2pNp7E/EGxA9hETo/szXz25buCKPJKtw7ppgUVzYvmFwqRdDytNFPc5ct jK/vbyWfOujqUUGLa+odrn4v56Glzfg87jPZrz3v89ZpQoOYqCeOPN9dVImtzf8Dii9idrrZoDj7 Ekx30gZB50nqDNBpayqAw25zZ9lD7h1uJv3UYGWlyeEeXk4ONCnWI3hp2lFQKd+d3ynuNyAYDpO3 O3DxLtzy6BFW0U6zZF/hZCOGFKtacKAxBtodCEvEW8SUM38VzVJWmteJnOVv0jT3rBgpZDp4GxYy 9wBtUv+21nyc695668SpW5VtPbFHBW2pHOrxG5MfBUhZwPTWNWqYFTv5gP3juQU+pS8303KdUQAX pjHUS4952vPEXBe+KvuKNEGPEQHTKS9c94OyQeUwEIF3outtR4WHttOtPTHB1+AB5kPAOd7eQIsU kM7zd6Gli4a7vC42eb2mZIDcQhELRvY36Ns1Dq90GRBGF7aRBzDnDwmEg/vyPI31i3JtlXDZabbY g= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:d0c0:200:0:1c7b:a6ff:fee0:8ea4; envelope-from=neither@nut.email; helo=mailgate02.uberspace.is X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @nut.email) X-ZM-MESSAGEID: 1747668346844116600 Content-Type: text/plain; charset="utf-8" We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for ARM (and Aarch64) targets. We decided to treat the (V)IRQ, (VI/VF)NMI, (V)FIQ and VSERR exceptions as interrupts since they are, presumably, async in nature. Signed-off-by: Julian Ganz --- target/arm/helper.c | 24 ++++++++++++++++++++++++ target/arm/tcg/m_helper.c | 18 ++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7631210287..06070441a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #endif #include "cpregs.h" #include "target/arm/gtimer.h" +#include "qemu/plugin.h" =20 #define HELPER_H "tcg/helper.h" #include "exec/helper-proto.h.inc" @@ -10214,6 +10215,24 @@ static void take_aarch32_exception(CPUARMState *en= v, int new_mode, } } =20 +static void arm_do_plugin_vcpu_interrupt_cb(CPUState *cs, uint64_t from) +{ + switch (cs->exception_index) { + case EXCP_IRQ: + case EXCP_VIRQ: + case EXCP_NMI: + case EXCP_VINMI: + case EXCP_FIQ: + case EXCP_VFIQ: + case EXCP_VFNMI: + case EXCP_VSERR: + qemu_plugin_vcpu_interrupt_cb(cs, from); + break; + default: + qemu_plugin_vcpu_exception_cb(cs, from); + } +} + static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) { /* @@ -10880,6 +10899,7 @@ void arm_cpu_do_interrupt(CPUState *cs) ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; unsigned int new_el =3D env->exception.target_el; + uint64_t last_pc =3D env->pc; =20 assert(!arm_feature(env, ARM_FEATURE_M)); =20 @@ -10896,6 +10916,7 @@ void arm_cpu_do_interrupt(CPUState *cs) if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { arm_handle_psci_call(cpu); qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; } =20 @@ -10907,6 +10928,7 @@ void arm_cpu_do_interrupt(CPUState *cs) #ifdef CONFIG_TCG if (cs->exception_index =3D=3D EXCP_SEMIHOST) { tcg_handle_semihosting(cs); + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; } #endif @@ -10932,6 +10954,8 @@ void arm_cpu_do_interrupt(CPUState *cs) if (!kvm_enabled()) { cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; } + + arm_do_plugin_vcpu_interrupt_cb(cs, last_pc); } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 6614719832..bcb4aae0d5 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -23,6 +23,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/intc/armv7m_nvic.h" #endif +#include "qemu/plugin.h" =20 static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val) @@ -2185,6 +2186,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) CPUARMState *env =3D &cpu->env; uint32_t lr; bool ignore_stackfaults; + uint64_t last_pc =3D env->pc; =20 arm_log_exception(cs); =20 @@ -2352,6 +2354,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) g_assert_not_reached(); #endif env->regs[15] +=3D env->thumb ? 2 : 4; + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; case EXCP_BKPT: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); @@ -2418,6 +2421,21 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) =20 ignore_stackfaults =3D v7m_push_stack(cpu); v7m_exception_taken(cpu, lr, false, ignore_stackfaults); + + switch (cs->exception_index) { + case EXCP_IRQ: + case EXCP_VIRQ: + case EXCP_NMI: + case EXCP_VINMI: + case EXCP_FIQ: + case EXCP_VFIQ: + case EXCP_VFNMI: + case EXCP_VSERR: + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); + break; + default: + qemu_plugin_vcpu_exception_cb(cs, last_pc); + } } =20 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) --=20 2.49.0