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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Bernhard Beschow , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?B?SGVydsOp?= Poussineau , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Aurelien Jarno Subject: [PULL v2 42/78] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697744550113100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bernhard Beschow Avoid assigning the private member of struct PIIX3State from outside which = goes against best QOM practices. Instead, implement best QOM practice by adding = an "isa-irqs" array property to TYPE_PIIX3_DEVICE and assign it in board code,= i.e. from outside. Signed-off-by: Bernhard Beschow Message-Id: <20231007123843.127151-6-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/southbridge/piix.h | 2 +- hw/i386/pc_piix.c | 7 ++++++- hw/isa/piix3.c | 2 ++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 2317bb7974..bb898c6c88 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -46,7 +46,7 @@ struct PIIXState { #endif uint64_t pic_levels; =20 - qemu_irq *pic; + qemu_irq pic[ISA_NUM_IRQS]; =20 /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index a003923788..4dc7298c15 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -263,10 +263,15 @@ static void pc_init1(MachineState *machine, if (pcmc->pci_enabled) { PIIX3State *piix3; PCIDevice *pci_dev; + DeviceState *dev; + size_t i; =20 pci_dev =3D pci_new_multifunction(-1, TYPE_PIIX3_DEVICE); piix3 =3D PIIX3_PCI_DEVICE(pci_dev); - piix3->pic =3D x86ms->gsi; + dev =3D DEVICE(pci_dev); + for (i =3D 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); + } pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); =20 if (xen_enabled()) { diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 7240c91440..c17547a2c0 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -312,6 +312,8 @@ static void pci_piix3_init(Object *obj) { PIIX3State *d =3D PIIX3_PCI_DEVICE(obj); =20 + qdev_init_gpio_out_named(DEVICE(obj), d->pic, "isa-irqs", ISA_NUM_IRQS= ); + object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } =20 --=20 MST