From nobody Sun Nov 24 23:25:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1720095454; cv=none; d=zohomail.com; s=zohoarc; b=OBeM2OiCiwo3TajG9mqREa8SyADhL7fevpli8o6jPDkdPy6KoKm1iwbIUYladm9CjOZaVnWvUgQc3LwlzaQwg6V8pxqIfhJLfhTr3QfiCIlnLozvtWFE2vJdX1r6MIg5mF7//uh4NROlj08+2cvVLr6tQHRhNb+pPVCeakjIkY0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720095454; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=llrJ0fioMvZ2Dz1eTwAi014ZiA1w9XkdIPsyaQw1FxU=; b=nuU/HLlUoAbEkegPz1a8pKirXNEn7q4fGLmMd7QCLbO/X33FmdiqdWZvvEYzZbQXIIb41a8Kc/iqWnV8dCn1SwyokzUHXCMgMMgc87COXcAtJ44jSiVe+TEnQcH24d2nUy54RDBayEsZBunjV2yF0jEfvJV1cguNKLDjK9z2axE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720095454599406.19404194954313; Thu, 4 Jul 2024 05:17:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPLOz-0008Vr-Uo; Thu, 04 Jul 2024 08:17:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPLOC-0007vX-Fn for qemu-devel@nongnu.org; Thu, 04 Jul 2024 08:16:41 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sPLNg-0002RQ-My for qemu-devel@nongnu.org; Thu, 04 Jul 2024 08:16:23 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4264a3847b6so3889795e9.0 for ; Thu, 04 Jul 2024 05:16:06 -0700 (PDT) Received: from localhost.localdomain (adsl-241.37.6.160.tellas.gr. [37.6.160.241]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a2ca5casm22471015e9.32.2024.07.04.05.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 05:16:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720095365; x=1720700165; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=llrJ0fioMvZ2Dz1eTwAi014ZiA1w9XkdIPsyaQw1FxU=; b=HqOZ0JbhsSG7oG+VWtKDX9otRjuX0aJe1gA3eJY/SHZ4cZyqp5A2kioGy1m6qguAFo i9UzbQi0u/zYNl8XnlK/j24HhGdHBHJSlqL9wSVeprpWyKnsO9XkTIMtz3QwFh3rcKy0 O7sX+xkvL4FyOnoqfhKe6CKcHn/DK1mYGQA1EHq4jimrRQMUKRQDXGh81ZWJWP0FplMU aGOuxS1vXFkYmNTbnOLdQ6BVKdzLCUgZltd7AEPxkYk7JpxoUGaNf8FWui07QKsuYjFX g6zM7NLea2TM09D3QpyghXR/LdFY4I3NC1HxhY/nObDprV0mbEJ+8K6SEC9tJRNrxX4m WsVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720095365; x=1720700165; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=llrJ0fioMvZ2Dz1eTwAi014ZiA1w9XkdIPsyaQw1FxU=; b=GoYfkxN5hhtxHqlMdiztmmhTJlRo4/mq5C8rw4pwTWRrJNXkALQ18hZwrYjo/+lZ2A 36jA39E26ZIzj7G91QjWQQPG7wbczSE5MyDMc1T//InLZDDn6sV9FP8YIcomzi9Cv09C Vyt7ox7Uml9gHwkC/4FsaMwmdyLR3xf9s5G0aiAKgX656CdDqj4YHIeBuTdkbSQmMG6p 2tCLMMIhhphbb62k0ciR+Qfx7VZVpnpOHPtp1IAjkHgkwtHtmdQOMDDk6JdJexFtVnHE Mtn14dVb/6hO7mVFViwJkqcrX1QqQFdf7Hip77FvY7fQAZg9DRJyturAYV2CVsTKU4xw B2Lg== X-Gm-Message-State: AOJu0Yy3sTA6ajPlk1dHID4sD4+uuMrTR5Z2OhyneM7NGOhe7lleUqoG CSbOaD7frpu5ufzou4GrxV+IHZdAlqNqwWmX6jIX5CCGT9h0wOThmS+PbS90OIpmTsCwumkwwfg DDsg= X-Google-Smtp-Source: AGHT+IH82NCyVSt8c068S8QWbQVsJHz6DtwE2K7mP3JYLpr1Uz5fDaL9zfTrorZXV7nAd6YfHocNng== X-Received: by 2002:a05:600c:4da2:b0:425:77ad:93cb with SMTP id 5b1f17b1804b1-4264a3cc8b0mr9943445e9.2.1720095364721; Thu, 04 Jul 2024 05:16:04 -0700 (PDT) From: Manos Pitsidianakis To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Mads Ynddal , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Gustavo Romero , Pierrick Bouvier , rowan.hart@intel.com, Richard Henderson , Paolo Bonzini Subject: [RFC PATCH v4 4/7] rust: add PL011 device model Date: Thu, 4 Jul 2024 15:15:40 +0300 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720095456495100013 Content-Type: text/plain; charset="utf-8" This commit adds a re-implementation of hw/char/pl011.c in Rust. How to build: 1. Make sure rust, cargo and bindgen (cargo install bindgen-cli) are installed 2. Configure a QEMU build with: --enable-system --target-list=3Daarch64-softmmu --enable-with-rust 3. Launching a VM with qemu-system-aarch64 should use the Rust version of the pl011 device (unless it is not set up so in hw/arm/virt.c; the type of the UART device is hardcoded). To confirm, inspect `info qom-tree` in the monitor and look for an `x-pl011-rust` device. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 5 + meson.build | 4 + rust/meson.build | 2 + rust/pl011/.gitignore | 2 + rust/pl011/Cargo.lock | 125 ++++++++ rust/pl011/Cargo.toml | 67 ++++ rust/pl011/README.md | 31 ++ rust/pl011/deny.toml | 57 ++++ rust/pl011/meson.build | 7 + rust/pl011/rustfmt.toml | 1 + rust/pl011/src/definitions.rs | 39 +++ rust/pl011/src/device.rs | 509 ++++++++++++++++++++++++++++++ rust/pl011/src/device_class.rs | 48 +++ rust/pl011/src/lib.rs | 556 +++++++++++++++++++++++++++++++++ rust/pl011/src/memory_ops.rs | 45 +++ 15 files changed, 1498 insertions(+) create mode 100644 rust/pl011/.gitignore create mode 100644 rust/pl011/Cargo.lock create mode 100644 rust/pl011/Cargo.toml create mode 100644 rust/pl011/README.md create mode 100644 rust/pl011/deny.toml create mode 100644 rust/pl011/meson.build create mode 120000 rust/pl011/rustfmt.toml create mode 100644 rust/pl011/src/definitions.rs create mode 100644 rust/pl011/src/device.rs create mode 100644 rust/pl011/src/device_class.rs create mode 100644 rust/pl011/src/lib.rs create mode 100644 rust/pl011/src/memory_ops.rs diff --git a/MAINTAINERS b/MAINTAINERS index 8598d38eae..fedee0ddef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1186,6 +1186,11 @@ F: include/hw/*/microbit*.h F: tests/qtest/microbit-test.c F: docs/system/arm/nrf.rst =20 +ARM PL011 Rust device +M: Manos Pitsidianakis +S: Maintained +F: rust/pl011/ + AVR Machines ------------- =20 diff --git a/meson.build b/meson.build index 71011fd3b3..945ce6aaaf 100644 --- a/meson.build +++ b/meson.build @@ -296,6 +296,10 @@ if get_option('with_rust').allowed() endif with_rust =3D cargo.found() =20 +if with_rust + subdir('rust') +endif + # default flags for all hosts # We use -fwrapv to tell the compiler that we require a C dialect where # left shift of signed integers is well defined and has the expected diff --git a/rust/meson.build b/rust/meson.build index 5fdc2621a3..21115ac56d 100644 --- a/rust/meson.build +++ b/rust/meson.build @@ -93,6 +93,8 @@ subdir('qemu-api') # bindgen dependency is declared. rust_hw_target_list =3D {} =20 +subdir('pl011') + foreach rust_hw_target, rust_hws: rust_hw_target_list foreach rust_hw_dev: rust_hws crate_metadata =3D { diff --git a/rust/pl011/.gitignore b/rust/pl011/.gitignore new file mode 100644 index 0000000000..71eaff2035 --- /dev/null +++ b/rust/pl011/.gitignore @@ -0,0 +1,2 @@ +# Ignore generated bindings file overrides. +src/bindings.rs.inc diff --git a/rust/pl011/Cargo.lock b/rust/pl011/Cargo.lock new file mode 100644 index 0000000000..411bfed9c9 --- /dev/null +++ b/rust/pl011/Cargo.lock @@ -0,0 +1,125 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version =3D 3 + +[[package]] +name =3D "arbitrary-int" +version =3D "1.2.7" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c84fc003e338a6f69fbd4f7fe9f92b535ff13e9af8997f3b14b6ddff8b1d= f46d" + +[[package]] +name =3D "bilge" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "dc707ed8ebf81de5cd6c7f48f54b4c8621760926cdf35a57000747c512e6= 7b57" +dependencies =3D [ + "arbitrary-int", + "bilge-impl", +] + +[[package]] +name =3D "bilge-impl" +version =3D "0.2.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "feb11e002038ad243af39c2068c8a72bcf147acf05025dcdb916fcc000ad= b2d8" +dependencies =3D [ + "itertools", + "proc-macro-error", + "proc-macro2", + "quote", + "syn", +] + +[[package]] +name =3D "either" +version =3D "1.12.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "3dca9240753cf90908d7e4aac30f630662b02aebaa1b58a3cadabdb23385= b58b" + +[[package]] +name =3D "itertools" +version =3D "0.11.0" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "b1c173a5686ce8bfa551b3563d0c2170bf24ca44da99c7ca4bfdab5418c3= fe57" +dependencies =3D [ + "either", +] + +[[package]] +name =3D "pl011" +version =3D "0.1.0" +dependencies =3D [ + "arbitrary-int", + "bilge", + "bilge-impl", + "qemu_api", +] + +[[package]] +name =3D "proc-macro-error" +version =3D "1.0.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "da25490ff9892aab3fcf7c36f08cfb902dd3e71ca0f9f9517bea02a73a5c= e38c" +dependencies =3D [ + "proc-macro-error-attr", + "proc-macro2", + "quote", + "version_check", +] + +[[package]] +name =3D "proc-macro-error-attr" +version =3D "1.0.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "a1be40180e52ecc98ad80b184934baf3d0d29f979574e439af5a55274b35= f869" +dependencies =3D [ + "proc-macro2", + "quote", + "version_check", +] + +[[package]] +name =3D "proc-macro2" +version =3D "1.0.84" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "ec96c6a92621310b51366f1e28d05ef11489516e93be030060e5fc12024a= 49d6" +dependencies =3D [ + "unicode-ident", +] + +[[package]] +name =3D "qemu_api" +version =3D "0.1.0" + +[[package]] +name =3D "quote" +version =3D "1.0.36" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "0fa76aaf39101c457836aec0ce2316dbdc3ab723cdda1c6bd4e6ad4208ac= aca7" +dependencies =3D [ + "proc-macro2", +] + +[[package]] +name =3D "syn" +version =3D "2.0.66" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cd= cff5" +dependencies =3D [ + "proc-macro2", + "quote", + "unicode-ident", +] + +[[package]] +name =3D "unicode-ident" +version =3D "1.0.12" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0f= ee4b" + +[[package]] +name =3D "version_check" +version =3D "0.9.4" +source =3D "registry+https://github.com/rust-lang/crates.io-index" +checksum =3D "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e= 483f" diff --git a/rust/pl011/Cargo.toml b/rust/pl011/Cargo.toml new file mode 100644 index 0000000000..51f672d883 --- /dev/null +++ b/rust/pl011/Cargo.toml @@ -0,0 +1,67 @@ +[package] +name =3D "pl011" +version =3D "0.1.0" +edition =3D "2021" +authors =3D ["Manos Pitsidianakis "] +license =3D "GPL-2.0 OR GPL-3.0-or-later" +readme =3D "README.md" +homepage =3D "https://www.qemu.org" +description =3D "pl011 device model for QEMU" +repository =3D "https://gitlab.com/epilys/rust-for-qemu" +resolver =3D "2" +publish =3D false +keywords =3D [] +categories =3D [] + +[lib] +crate-type =3D ["staticlib"] + +# bilge deps included here to include them with docs +[dependencies] +arbitrary-int =3D { version =3D "1.2.7" } +bilge =3D { version =3D "0.2.0" } +bilge-impl =3D { version =3D "0.2.0" } +qemu_api =3D { path =3D "../qemu-api" } + +[lints] +[lints.rustdoc] +broken_intra_doc_links =3D "deny" +redundant_explicit_links =3D "deny" +[lints.clippy] +# lint groups +correctness =3D { level =3D "deny", priority =3D -1 } +suspicious =3D { level =3D "deny", priority =3D -1 } +complexity =3D { level =3D "deny", priority =3D -1 } +perf =3D { level =3D "deny", priority =3D -1 } +cargo =3D { level =3D "deny", priority =3D -1 } +nursery =3D { level =3D "deny", priority =3D -1 } +style =3D { level =3D "deny", priority =3D -1 } +# restriction group +dbg_macro =3D "deny" +rc_buffer =3D "deny" +as_underscore =3D "deny" +assertions_on_result_states =3D "deny" +# pedantic group +doc_markdown =3D "deny" +expect_fun_call =3D "deny" +borrow_as_ptr =3D "deny" +case_sensitive_file_extension_comparisons =3D "deny" +cast_lossless =3D "deny" +cast_ptr_alignment =3D "allow" +large_futures =3D "deny" +waker_clone_wake =3D "deny" +unused_enumerate_index =3D "deny" +unnecessary_fallible_conversions =3D "deny" +struct_field_names =3D "deny" +manual_hash_one =3D "deny" +into_iter_without_iter =3D "deny" +option_if_let_else =3D "deny" +missing_const_for_fn =3D "deny" +significant_drop_tightening =3D "deny" +multiple_crate_versions =3D "deny" +significant_drop_in_scrutinee =3D "deny" +cognitive_complexity =3D "deny" +missing_safety_doc =3D "allow" + +# Do not include in any global workspace +[workspace] diff --git a/rust/pl011/README.md b/rust/pl011/README.md new file mode 100644 index 0000000000..cd7dea3163 --- /dev/null +++ b/rust/pl011/README.md @@ -0,0 +1,31 @@ +# PL011 QEMU Device Model + +This library implements a device model for the PrimeCell=C2=AE UART (PL011) +device in QEMU. + +## Build static lib + +Host build target must be explicitly specified: + +```sh +cargo build --target x86_64-unknown-linux-gnu +``` + +Replace host target triplet if necessary. + +## Generate Rust documentation + +To generate docs for this crate, including private items: + +```sh +cargo doc --no-deps --document-private-items --target x86_64-unknown-linux= -gnu +``` + +To include direct dependencies like `bilge` (bitmaps for register types): + +```sh +cargo tree --depth 1 -e normal --prefix none \ + | cut -d' ' -f1 \ + | xargs printf -- '-p %s\n' \ + | xargs cargo doc --no-deps --document-private-items --target x86_64-unkn= own-linux-gnu +``` diff --git a/rust/pl011/deny.toml b/rust/pl011/deny.toml new file mode 100644 index 0000000000..3992380509 --- /dev/null +++ b/rust/pl011/deny.toml @@ -0,0 +1,57 @@ +# cargo-deny configuration file + +[graph] +targets =3D [ + "aarch64-unknown-linux-gnu", + "x86_64-unknown-linux-gnu", + "x86_64-apple-darwin", + "aarch64-apple-darwin", + "x86_64-pc-windows-gnu", + "aarch64-pc-windows-gnullvm", +] +#exclude =3D [] +all-features =3D false +no-default-features =3D false +#features =3D [] + +[output] +feature-depth =3D 1 + +[advisories] +db-path =3D "$CARGO_HOME/advisory-dbs" +db-urls =3D ["https://github.com/rustsec/advisory-db"] +ignore =3D [] + +[licenses] +allow =3D [ + "GPL-2.0", + "MIT", + "Apache-2.0", + "Unicode-DFS-2016", +] +confidence-threshold =3D 0.8 +exceptions =3D [] + +[licenses.private] +ignore =3D false +registries =3D [] + +[bans] +multiple-versions =3D "warn" +wildcards =3D "deny" +# The graph highlighting used when creating dotgraphs for crates +# with multiple versions +# * lowest-version - The path to the lowest versioned duplicate is highlig= hted +# * simplest-path - The path to the version with the fewest edges is highl= ighted +# * all - Both lowest-version and simplest-path are used +highlight =3D "all" +workspace-default-features =3D "allow" +external-default-features =3D "allow" +allow =3D [] +deny =3D [] + +[sources] +unknown-registry =3D "deny" +unknown-git =3D "deny" +allow-registry =3D ["https://github.com/rust-lang/crates.io-index"] +allow-git =3D [] diff --git a/rust/pl011/meson.build b/rust/pl011/meson.build new file mode 100644 index 0000000000..cbac0fd94d --- /dev/null +++ b/rust/pl011/meson.build @@ -0,0 +1,7 @@ +rust_pl011 =3D { + 'name': 'pl011', + 'dirname': 'pl011', + 'output': 'libpl011.a', + } + +rust_hw_target_list +=3D {'aarch64-softmmu': [rust_pl011]} diff --git a/rust/pl011/rustfmt.toml b/rust/pl011/rustfmt.toml new file mode 120000 index 0000000000..39f97b043b --- /dev/null +++ b/rust/pl011/rustfmt.toml @@ -0,0 +1 @@ +../rustfmt.toml \ No newline at end of file diff --git a/rust/pl011/src/definitions.rs b/rust/pl011/src/definitions.rs new file mode 100644 index 0000000000..5efe8ae7f0 --- /dev/null +++ b/rust/pl011/src/definitions.rs @@ -0,0 +1,39 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +//! Definitions required by QEMU when registering the device. + +use core::{mem::MaybeUninit, ptr::NonNull}; + +use qemu_api::bindings::*; + +use crate::{device::PL011State, device_class::pl011_class_init}; + +qemu_api::type_info! { + PL011_ARM_INFO: PL011State, + name: c"x-pl011-rust", + parent: TYPE_SYS_BUS_DEVICE, + instance_init: Some(pl011_init), + abstract_: false, + class_init: Some(pl011_class_init), +} + +#[used] +pub static VMSTATE_PL011: VMStateDescription =3D VMStateDescription { + name: PL011_ARM_INFO.name, + unmigratable: true, + ..unsafe { MaybeUninit::::zeroed().assume_init() } +}; + +#[no_mangle] +pub unsafe extern "C" fn pl011_init(obj: *mut Object) { + assert!(!obj.is_null()); + let mut state =3D NonNull::new_unchecked(obj.cast::()); + state.as_mut().init(); +} + +qemu_api::module_init! { + qom: register_type =3D> { + type_register_static(&PL011_ARM_INFO); + } +} diff --git a/rust/pl011/src/device.rs b/rust/pl011/src/device.rs new file mode 100644 index 0000000000..4aedd9582d --- /dev/null +++ b/rust/pl011/src/device.rs @@ -0,0 +1,509 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use core::{ + ffi::{c_int, c_uchar, c_uint, c_void, CStr}, + ptr::{addr_of, addr_of_mut, NonNull}, +}; + +use qemu_api::bindings::{self, *}; + +use crate::{ + definitions::PL011_ARM_INFO, + memory_ops::PL011_OPS, + registers::{self, Interrupt}, + RegisterOffset, +}; + +static PL011_ID_ARM: [c_uchar; 8] =3D [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0,= 0x05, 0xb1]; + +const DATA_BREAK: u32 =3D 1 << 10; + +/// QEMU sourced constant. +pub const PL011_FIFO_DEPTH: usize =3D 16_usize; + +#[repr(C)] +#[derive(Debug)] +/// PL011 Device Model in QEMU +pub struct PL011State { + pub parent_obj: SysBusDevice, + pub iomem: MemoryRegion, + pub readbuff: u32, + #[doc(alias =3D "fr")] + pub flags: registers::Flags, + #[doc(alias =3D "lcr")] + pub line_control: registers::LineControl, + #[doc(alias =3D "rsr")] + pub receive_status_error_clear: registers::ReceiveStatusErrorClear, + #[doc(alias =3D "cr")] + pub control: registers::Control, + pub dmacr: u32, + pub int_enabled: u32, + pub int_level: u32, + pub read_fifo: [u32; PL011_FIFO_DEPTH], + pub ilpr: u32, + pub ibrd: u32, + pub fbrd: u32, + pub ifl: u32, + pub read_pos: usize, + pub read_count: usize, + pub read_trigger: usize, + #[doc(alias =3D "chr")] + pub char_backend: CharBackend, + /// QEMU interrupts + /// + /// ```text + /// * sysbus MMIO region 0: device registers + /// * sysbus IRQ 0: `UARTINTR` (combined interrupt line) + /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line) + /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line) + /// * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line) + /// * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line) + /// * sysbus IRQ 5: `UARTEINTR` (error interrupt line) + /// ``` + #[doc(alias =3D "irq")] + pub interrupts: [qemu_irq; 6usize], + #[doc(alias =3D "clk")] + pub clock: NonNull, + #[doc(alias =3D "migrate_clk")] + pub migrate_clock: bool, +} + +#[used] +pub static CLK_NAME: &CStr =3D c"clk"; + +impl PL011State { + pub fn init(&mut self) { + unsafe { + memory_region_init_io( + addr_of_mut!(self.iomem), + addr_of_mut!(*self).cast::(), + &PL011_OPS, + addr_of_mut!(*self).cast::(), + PL011_ARM_INFO.name, + 0x1000, + ); + let sbd =3D addr_of_mut!(*self).cast::(); + let dev =3D addr_of_mut!(*self).cast::(); + sysbus_init_mmio(sbd, addr_of_mut!(self.iomem)); + for irq in self.interrupts.iter_mut() { + sysbus_init_irq(sbd, irq); + } + self.clock =3D NonNull::new(qdev_init_clock_in( + dev, + CLK_NAME.as_ptr(), + None, /* pl011_clock_update */ + addr_of_mut!(*self).cast::(), + ClockEvent_ClockUpdate, + )) + .unwrap(); + } + } + + pub fn read(&mut self, offset: hwaddr, _size: core::ffi::c_uint) -> u6= 4 { + use RegisterOffset::*; + + match RegisterOffset::try_from(offset) { + Err(v) if (0x3f8..0x400).contains(&v) =3D> { + u64::from(PL011_ID_ARM[((offset - 0xfe0) >> 2) as usize]) + } + Err(_) =3D> { + // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); + 0 + } + Ok(DR) =3D> { + // s->flags &=3D ~PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(false); + let c =3D self.read_fifo[self.read_pos]; + if self.read_count > 0 { + self.read_count -=3D 1; + self.read_pos =3D (self.read_pos + 1) & (self.fifo_dep= th() - 1); + } + if self.read_count =3D=3D 0 { + // self.flags |=3D PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(true); + } + if self.read_count + 1 =3D=3D self.read_trigger { + //self.int_level &=3D ~ INT_RX; + self.int_level &=3D !registers::INT_RX; + } + // Update error bits. + self.receive_status_error_clear =3D c.to_be_bytes()[3].int= o(); + self.update(); + unsafe { qemu_chr_fe_accept_input(&mut self.char_backend) = }; + c.into() + } + Ok(RSR) =3D> u8::from(self.receive_status_error_clear).into(), + Ok(FR) =3D> u16::from(self.flags).into(), + Ok(FBRD) =3D> self.fbrd.into(), + Ok(ILPR) =3D> self.ilpr.into(), + Ok(IBRD) =3D> self.ibrd.into(), + Ok(LCR_H) =3D> u16::from(self.line_control).into(), + Ok(CR) =3D> { + // We exercise our self-control. + u16::from(self.control).into() + } + Ok(FLS) =3D> self.ifl.into(), + Ok(IMSC) =3D> self.int_enabled.into(), + Ok(RIS) =3D> self.int_level.into(), + Ok(MIS) =3D> u64::from(self.int_level & self.int_enabled), + Ok(ICR) =3D> { + // "The UARTICR Register is the interrupt clear register a= nd is write-only" + // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, = UARTICR + 0 + } + Ok(DMACR) =3D> self.dmacr.into(), + } + } + + pub fn write(&mut self, offset: hwaddr, value: u64) { + // eprintln!("write offset {offset} value {value}"); + use RegisterOffset::*; + let value: u32 =3D value as u32; + match RegisterOffset::try_from(offset) { + Err(_bad_offset) =3D> { + eprintln!("write bad offset {offset} value {value}"); + } + Ok(DR) =3D> { + // ??? Check if transmitter is enabled. + let ch: u8 =3D value as u8; + // XXX this blocks entire thread. Rewrite to use + // qemu_chr_fe_write and background I/O callbacks + unsafe { + qemu_chr_fe_write_all(addr_of_mut!(self.char_backend),= &ch, 1); + } + self.loopback_tx(value); + self.int_level |=3D registers::INT_TX; + self.update(); + } + Ok(RSR) =3D> { + self.receive_status_error_clear =3D 0.into(); + } + Ok(FR) =3D> { + // flag writes are ignored + } + Ok(ILPR) =3D> { + self.ilpr =3D value; + } + Ok(IBRD) =3D> { + self.ibrd =3D value; + } + Ok(FBRD) =3D> { + self.fbrd =3D value; + } + Ok(LCR_H) =3D> { + let value =3D value as u16; + let new_val: registers::LineControl =3D value.into(); + // Reset the FIFO state on FIFO enable or disable + if bool::from(self.line_control.fifos_enabled()) + ^ bool::from(new_val.fifos_enabled()) + { + self.reset_fifo(); + } + if self.line_control.send_break() ^ new_val.send_break() { + let mut break_enable: c_int =3D new_val.send_break().i= nto(); + unsafe { + qemu_chr_fe_ioctl( + addr_of_mut!(self.char_backend), + CHR_IOCTL_SERIAL_SET_BREAK as i32, + addr_of_mut!(break_enable).cast::(), + ); + } + self.loopback_break(break_enable > 0); + } + self.line_control =3D new_val; + self.set_read_trigger(); + } + Ok(CR) =3D> { + // ??? Need to implement the enable bit. + let value =3D value as u16; + self.control =3D value.into(); + self.loopback_mdmctrl(); + } + Ok(FLS) =3D> { + self.ifl =3D value; + self.set_read_trigger(); + } + Ok(IMSC) =3D> { + self.int_enabled =3D value; + self.update(); + } + Ok(RIS) =3D> {} + Ok(MIS) =3D> {} + Ok(ICR) =3D> { + self.int_level &=3D !value; + self.update(); + } + Ok(DMACR) =3D> { + self.dmacr =3D value; + if value & 3 > 0 { + // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemente= d\n"); + eprintln!("pl011: DMA not implemented"); + } + } + } + } + + #[inline] + fn loopback_tx(&mut self, value: u32) { + if !self.loopback_enabled() { + return; + } + + // Caveat: + // + // In real hardware, TX loopback happens at the serial-bit level + // and then reassembled by the RX logics back into bytes and placed + // into the RX fifo. That is, loopback happens after TX fifo. + // + // Because the real hardware TX fifo is time-drained at the frame + // rate governed by the configured serial format, some loopback + // bytes in TX fifo may still be able to get into the RX fifo + // that could be full at times while being drained at software + // pace. + // + // In such scenario, the RX draining pace is the major factor + // deciding which loopback bytes get into the RX fifo, unless + // hardware flow-control is enabled. + // + // For simplicity, the above described is not emulated. + self.put_fifo(value); + } + + fn loopback_mdmctrl(&mut self) { + if !self.loopback_enabled() { + return; + } + + /* + * Loopback software-driven modem control outputs to modem status = inputs: + * FR.RI <=3D CR.Out2 + * FR.DCD <=3D CR.Out1 + * FR.CTS <=3D CR.RTS + * FR.DSR <=3D CR.DTR + * + * The loopback happens immediately even if this call is triggered + * by setting only CR.LBE. + * + * CTS/RTS updates due to enabled hardware flow controls are not + * dealt with here. + */ + + //fr =3D s->flags & ~(PL011_FLAG_RI | PL011_FLAG_DCD | + // PL011_FLAG_DSR | PL011_FLAG_CTS); + //fr |=3D (cr & CR_OUT2) ? PL011_FLAG_RI : 0; + //fr |=3D (cr & CR_OUT1) ? PL011_FLAG_DCD : 0; + //fr |=3D (cr & CR_RTS) ? PL011_FLAG_CTS : 0; + //fr |=3D (cr & CR_DTR) ? PL011_FLAG_DSR : 0; + // + self.flags.set_ring_indicator(self.control.out_2()); + self.flags.set_data_carrier_detect(self.control.out_1()); + self.flags.set_clear_to_send(self.control.request_to_send()); + self.flags + .set_data_set_ready(self.control.data_transmit_ready()); + + // Change interrupts based on updated FR + let mut il =3D self.int_level; + + il &=3D !Interrupt::MS; + //il |=3D (fr & PL011_FLAG_DSR) ? INT_DSR : 0; + //il |=3D (fr & PL011_FLAG_DCD) ? INT_DCD : 0; + //il |=3D (fr & PL011_FLAG_CTS) ? INT_CTS : 0; + //il |=3D (fr & PL011_FLAG_RI) ? INT_RI : 0; + + if self.flags.data_set_ready() { + il |=3D Interrupt::DSR as u32; + } + if self.flags.data_carrier_detect() { + il |=3D Interrupt::DCD as u32; + } + if self.flags.clear_to_send() { + il |=3D Interrupt::CTS as u32; + } + if self.flags.ring_indicator() { + il |=3D Interrupt::RI as u32; + } + self.int_level =3D il; + self.update(); + } + + fn loopback_break(&mut self, enable: bool) { + if enable { + self.loopback_tx(DATA_BREAK); + } + } + + fn set_read_trigger(&mut self) { + //#if 0 + // /* The docs say the RX interrupt is triggered when the FIFO = exceeds + // the threshold. However linux only reads the FIFO in resp= onse to an + // interrupt. Triggering the interrupt when the FIFO is non= -empty seems + // to make things work. */ + // if (s->lcr & LCR_FEN) + // s->read_trigger =3D (s->ifl >> 1) & 0x1c; + // else + //#endif + self.read_trigger =3D 1; + } + + pub fn realize(&mut self) { + unsafe { + qemu_chr_fe_set_handlers( + addr_of_mut!(self.char_backend), + Some(pl011_can_receive), + Some(pl011_receive), + Some(pl011_event), + None, + addr_of_mut!(*self).cast::(), + core::ptr::null_mut(), + true, + ); + } + } + + pub fn reset(&mut self) { + self.line_control.reset(); + self.receive_status_error_clear.reset(); + self.dmacr =3D 0; + self.int_enabled =3D 0; + self.int_level =3D 0; + self.ilpr =3D 0; + self.ibrd =3D 0; + self.fbrd =3D 0; + self.read_trigger =3D 1; + self.ifl =3D 0x12; + self.control.reset(); + self.flags =3D 0.into(); + self.reset_fifo(); + } + + pub fn reset_fifo(&mut self) { + self.read_count =3D 0; + self.read_pos =3D 0; + + /* Reset FIFO flags */ + self.flags.reset(); + } + + pub fn can_receive(&self) -> bool { + // trace_pl011_can_receive(s->lcr, s->read_count, r); + self.read_count < self.fifo_depth() + } + + pub fn event(&mut self, event: QEMUChrEvent) { + if event =3D=3D bindings::QEMUChrEvent_CHR_EVENT_BREAK && !self.fi= fo_enabled() { + self.put_fifo(DATA_BREAK); + self.receive_status_error_clear.set_break_error(true); + } + } + + #[inline] + pub fn fifo_enabled(&self) -> bool { + matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO) + } + + #[inline] + pub fn loopback_enabled(&self) -> bool { + self.control.enable_loopback() + } + + #[inline] + pub fn fifo_depth(&self) -> usize { + // Note: FIFO depth is expected to be power-of-2 + if self.fifo_enabled() { + return PL011_FIFO_DEPTH; + } + 1 + } + + pub fn put_fifo(&mut self, value: c_uint) { + let depth =3D self.fifo_depth(); + assert!(depth > 0); + let slot =3D (self.read_pos + self.read_count) & (depth - 1); + self.read_fifo[slot] =3D value; + self.read_count +=3D 1; + // s->flags &=3D ~PL011_FLAG_RXFE; + self.flags.set_receive_fifo_empty(false); + if self.read_count =3D=3D depth { + //s->flags |=3D PL011_FLAG_RXFF; + self.flags.set_receive_fifo_full(true); + } + + if self.read_count =3D=3D self.read_trigger { + self.int_level |=3D registers::INT_RX; + self.update(); + } + } + + pub fn update(&mut self) { + let flags =3D self.int_level & self.int_enabled; + for (irq, i) in self.interrupts.iter().zip(IRQMASK) { + unsafe { qemu_set_irq(*irq, i32::from(flags & i !=3D 0)) }; + } + } +} + +/// Which bits in the interrupt status matter for each outbound IRQ line ? +pub const IRQMASK: [u32; 6] =3D [ + /* combined IRQ */ + Interrupt::E + | Interrupt::MS + | Interrupt::RT as u32 + | Interrupt::TX as u32 + | Interrupt::RX as u32, + Interrupt::RX as u32, + Interrupt::TX as u32, + Interrupt::RT as u32, + Interrupt::MS, + Interrupt::E, +]; + +#[no_mangle] +pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int { + assert!(!opaque.is_null()); + let state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_ref().can_receive().into() +} + +#[no_mangle] +pub unsafe extern "C" fn pl011_receive( + opaque: *mut core::ffi::c_void, + buf: *const u8, + size: core::ffi::c_int, +) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + if state.as_ref().loopback_enabled() { + return; + } + if size > 0 { + assert!(!buf.is_null()); + state.as_mut().put_fifo(*buf.cast::()) + } +} + +#[no_mangle] +pub unsafe extern "C" fn pl011_event(opaque: *mut core::ffi::c_void, event= : QEMUChrEvent) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().event(event) +} + +#[no_mangle] +pub unsafe extern "C" fn rust_pl011_create( + addr: u64, + irq: qemu_irq, + chr: *mut Chardev, +) -> *mut DeviceState { + let dev: *mut DeviceState =3D unsafe { qdev_new(PL011_ARM_INFO.name) }; + assert!(!dev.is_null()); + let sysbus: *mut SysBusDevice =3D dev as *mut SysBusDevice; + + unsafe { + qdev_prop_set_chr(dev, bindings::TYPE_CHARDEV.as_ptr(), chr); + sysbus_realize_and_unref(sysbus, addr_of!(error_fatal) as *mut *mu= t Error); + sysbus_mmio_map(sysbus, 0, addr); + sysbus_connect_irq(sysbus, 0, irq); + } + dev +} diff --git a/rust/pl011/src/device_class.rs b/rust/pl011/src/device_class.rs new file mode 100644 index 0000000000..a886731107 --- /dev/null +++ b/rust/pl011/src/device_class.rs @@ -0,0 +1,48 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use core::ptr::NonNull; + +use qemu_api::bindings::*; + +use crate::{definitions::VMSTATE_PL011, device::PL011State}; + +qemu_api::declare_properties! { + PL011_PROPERTIES, + qemu_api::define_property!( + c"chardev", + PL011State, + char_backend, + unsafe { &qdev_prop_chr }, + CharBackend + ), + qemu_api::define_property!( + c"migrate-clk", + PL011State, + migrate_clock, + unsafe { &qdev_prop_bool }, + bool + ), +} + +qemu_api::device_class_init! { + pl011_class_init, + props =3D> PL011_PROPERTIES, + realize_fn =3D> Some(pl011_realize), + reset_fn =3D> Some(pl011_reset), + vmsd =3D> VMSTATE_PL011, +} + +#[no_mangle] +pub unsafe extern "C" fn pl011_realize(dev: *mut DeviceState, _errp: *mut = *mut Error) { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().realize(); +} + +#[no_mangle] +pub unsafe extern "C" fn pl011_reset(dev: *mut DeviceState) { + assert!(!dev.is_null()); + let mut state =3D NonNull::new_unchecked(dev.cast::()); + state.as_mut().reset(); +} diff --git a/rust/pl011/src/lib.rs b/rust/pl011/src/lib.rs new file mode 100644 index 0000000000..ec7ed04fc0 --- /dev/null +++ b/rust/pl011/src/lib.rs @@ -0,0 +1,556 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later +// +// PL011 QEMU Device Model +// +// This library implements a device model for the PrimeCell=C2=AE UART (PL= 011) +// device in QEMU. +// +#![doc =3D include_str!("../README.md")] +//! # Library crate +//! +//! See [`PL011State`](crate::device::PL011State) for the device model typ= e and +//! the [`registers`] module for register types. + +pub mod definitions; +pub mod device; +pub mod device_class; +pub mod memory_ops; + +/// Offset of each register from the base memory address of the device. +/// +/// # Source +/// ARM DDI 0183G, Table 3-1 p.3-3 +#[doc(alias =3D "offset")] +#[allow(non_camel_case_types)] +#[repr(u64)] +#[derive(Debug)] +pub enum RegisterOffset { + /// Data Register + /// + /// A write to this register initiates the actual data transmission + #[doc(alias =3D "UARTDR")] + DR =3D 0x000, + /// Receive Status Register or Error Clear Register + #[doc(alias =3D "UARTRSR")] + #[doc(alias =3D "UARTECR")] + RSR =3D 0x004, + /// Flag Register + /// + /// A read of this register shows if transmission is complete + #[doc(alias =3D "UARTFR")] + FR =3D 0x018, + /// Fractional Baud Rate Register + /// + /// responsible for baud rate speed + #[doc(alias =3D "UARTFBRD")] + FBRD =3D 0x028, + /// `IrDA` Low-Power Counter Register + #[doc(alias =3D "UARTILPR")] + ILPR =3D 0x020, + /// Integer Baud Rate Register + /// + /// Responsible for baud rate speed + #[doc(alias =3D "UARTIBRD")] + IBRD =3D 0x024, + /// line control register (data frame format) + #[doc(alias =3D "UARTLCR_H")] + LCR_H =3D 0x02C, + /// Toggle UART, transmission or reception + #[doc(alias =3D "UARTCR")] + CR =3D 0x030, + /// Interrupt FIFO Level Select Register + #[doc(alias =3D "UARTIFLS")] + FLS =3D 0x034, + /// Interrupt Mask Set/Clear Register + #[doc(alias =3D "UARTIMSC")] + IMSC =3D 0x038, + /// Raw Interrupt Status Register + #[doc(alias =3D "UARTRIS")] + RIS =3D 0x03C, + /// Masked Interrupt Status Register + #[doc(alias =3D "UARTMIS")] + MIS =3D 0x040, + /// Interrupt Clear Register + #[doc(alias =3D "UARTICR")] + ICR =3D 0x044, + /// DMA control Register + #[doc(alias =3D "UARTDMACR")] + DMACR =3D 0x048, + ///// Reserved, offsets `0x04C` to `0x07C`. + //Reserved =3D 0x04C, +} + +impl core::convert::TryFrom for RegisterOffset { + type Error =3D u64; + + fn try_from(value: u64) -> Result { + macro_rules! case { + ($($discriminant:ident),*$(,)*) =3D> { + /* check that matching on all macro arguments compiles, wh= ich means we are not + * missing any enum value; if the type definition ever cha= nges this will stop + * compiling. + */ + const fn _assert_exhaustive(val: RegisterOffset) { + match val { + $(RegisterOffset::$discriminant =3D> (),)* + } + } + + match value { + $(x if x =3D=3D Self::$discriminant as u64 =3D> Ok(Sel= f::$discriminant),)* + _ =3D> Err(value), + } + } + } + case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, = MIS, ICR, DMACR } + } +} + +pub mod registers { + //! Device registers exposed as typed structs which are backed by arbi= trary + //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. + //! + //! All PL011 registers are essentially 32-bit wide, but are typed her= e as + //! bitmaps with only the necessary width. That is, if a struct bitmap + //! in this module is for example 16 bits long, it should be conceived + //! as a 32-bit register where the unmentioned higher bits are always + //! unused thus treated as zero when read or written. + use bilge::prelude::*; + + // TODO: FIFO Mode has different semantics + /// Data Register, `UARTDR` + /// + /// The `UARTDR` register is the data register. + /// + /// For words to be transmitted: + /// + /// - if the FIFOs are enabled, data written to this location is pushe= d onto + /// the transmit + /// FIFO + /// - if the FIFOs are not enabled, data is stored in the transmitter + /// holding register (the + /// bottom word of the transmit FIFO). + /// + /// The write operation initiates transmission from the UART. The data= is + /// prefixed with a start bit, appended with the appropriate parity bit + /// (if parity is enabled), and a stop bit. The resultant word is then + /// transmitted. + /// + /// For received words: + /// + /// - if the FIFOs are enabled, the data byte and the 4-bit status (br= eak, + /// frame, parity, + /// and overrun) is pushed onto the 12-bit wide receive FIFO + /// - if the FIFOs are not enabled, the data byte and status are store= d in + /// the receiving + /// holding register (the bottom word of the receive FIFO). + /// + /// The received data byte is read by performing reads from the `UARTD= R` + /// register along with the corresponding status information. The stat= us + /// information can also be read by a read of the `UARTRSR/UARTECR` + /// register. + /// + /// # Note + /// + /// You must disable the UART before any of the control registers are + /// reprogrammed. When the UART is disabled in the middle of + /// transmission or reception, it completes the current character befo= re + /// stopping. + /// + /// # Source + /// ARM DDI 0183G 3.3.1 Data Register, UARTDR + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + #[doc(alias =3D "UARTDR")] + pub struct Data { + _reserved: u4, + pub data: u8, + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + } + + // TODO: FIFO Mode has different semantics + /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR` + /// + /// The UARTRSR/UARTECR register is the receive status register/error = clear + /// register. Receive status can also be read from the `UARTRSR` + /// register. If the status is read from this register, then the status + /// information for break, framing and parity corresponds to the + /// data character read from the [Data register](Data), `UARTDR` prior= to + /// reading the UARTRSR register. The status information for overrun is + /// set immediately when an overrun condition occurs. + /// + /// + /// # Note + /// The received data character must be read first from the [Data + /// Register](Data), `UARTDR` before reading the error status associat= ed + /// with that data character from the `UARTRSR` register. This read + /// sequence cannot be reversed, because the `UARTRSR` register is + /// updated only when a read occurs from the `UARTDR` register. Howeve= r, + /// the status information can also be obtained by reading the `UARTDR` + /// register + /// + /// # Source + /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, + /// UARTRSR/UARTECR + #[bitsize(8)] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct ReceiveStatusErrorClear { + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + _reserved_unpredictable: u4, + } + + impl ReceiveStatusErrorClear { + pub fn reset(&mut self) { + // All the bits are cleared to 0 on reset. + *self =3D 0.into(); + } + } + + impl Default for ReceiveStatusErrorClear { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Flag Register, `UARTFR` + #[doc(alias =3D "UARTFR")] + pub struct Flags { + /// CTS Clear to send. This bit is the complement of the UART clea= r to + /// send, `nUARTCTS`, modem status input. That is, the bit is 1 + /// when `nUARTCTS` is LOW. + pub clear_to_send: bool, + /// DSR Data set ready. This bit is the complement of the UART dat= a set + /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 w= hen + /// `nUARTDSR` is LOW. + pub data_set_ready: bool, + /// DCD Data carrier detect. This bit is the complement of the UAR= T data + /// carrier detect, `nUARTDCD`, modem status input. That is, the b= it is + /// 1 when `nUARTDCD` is LOW. + pub data_carrier_detect: bool, + /// BUSY UART busy. If this bit is set to 1, the UART is busy + /// transmitting data. This bit remains set until the complete + /// byte, including all the stop bits, has been sent from the + /// shift register. This bit is set as soon as the transmit FIFO + /// becomes non-empty, regardless of whether the UART is enabled + /// or not. + pub busy: bool, + /// RXFE Receive FIFO empty. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the receive holding + /// register is empty. If the FIFO is enabled, the RXFE bit is + /// set when the receive FIFO is empty. + pub receive_fifo_empty: bool, + /// TXFF Transmit FIFO full. The meaning of this bit depends on the + /// state of the FEN bit in the UARTLCR_H register. If the FIFO + /// is disabled, this bit is set when the transmit holding + /// register is full. If the FIFO is enabled, the TXFF bit is + /// set when the transmit FIFO is full. + pub transmit_fifo_full: bool, + /// RXFF Receive FIFO full. The meaning of this bit depends on the= state + /// of the FEN bit in the UARTLCR_H register. If the FIFO is + /// disabled, this bit is set when the receive holding register + /// is full. If the FIFO is enabled, the RXFF bit is set when + /// the receive FIFO is full. + pub receive_fifo_full: bool, + /// Transmit FIFO empty. The meaning of this bit depends on the st= ate of + /// the FEN bit in the [Line Control register](LineControl), + /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the + /// transmit holding register is empty. If the FIFO is enabled, + /// the TXFE bit is set when the transmit FIFO is empty. This + /// bit does not indicate if there is data in the transmit shift + /// register. + pub transmit_fifo_empty: bool, + /// `RI`, is `true` when `nUARTRI` is `LOW`. + pub ring_indicator: bool, + _reserved_zero_no_modify: u7, + } + + impl Flags { + pub fn reset(&mut self) { + // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE a= re 1 + self.set_receive_fifo_full(false); + self.set_transmit_fifo_full(false); + self.set_busy(false); + self.set_receive_fifo_empty(true); + self.set_transmit_fifo_empty(true); + } + } + + impl Default for Flags { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + #[bitsize(16)] + #[derive(Clone, Copy, DebugBits, FromBits)] + /// Line Control Register, `UARTLCR_H` + #[doc(alias =3D "UARTLCR_H")] + pub struct LineControl { + /// 15:8 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u8, + /// 7 SPS Stick parity select. + /// 0 =3D stick parity is disabled + /// 1 =3D either: + /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt= ed and checked + /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is + /// transmitted and checked as a 0. This bit has no effect when + /// the PEN bit disables parity checking and generation. See Table= 3-11 + /// on page 3-14 for the parity truth table. + pub sticky_parity: bool, + /// WLEN Word length. These bits indicate the number of data bits + /// transmitted or received in a frame as follows: b11 =3D 8 bits + /// b10 =3D 7 bits + /// b01 =3D 6 bits + /// b00 =3D 5 bits. + pub word_length: WordLength, + /// FEN Enable FIFOs: + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO + /// buffers are enabled (FIFO mode). + pub fifos_enabled: Mode, + /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop= bits + /// are transmitted at the end of the frame. The receive + /// logic does not check for two stop bits being received. + pub two_stops_bits: bool, + /// EPS Even parity select. Controls the type of parity the UART u= ses + /// during transmission and reception: + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + /// This bit has no effect when the `PEN` bit disables parity chec= king + /// and generation. See Table 3-11 on page 3-14 for the parity + /// truth table. + pub parity: Parity, + /// 1 PEN Parity enable: + /// + /// - 0 =3D parity is disabled and no parity bit added to the data= frame + /// - 1 =3D parity checking and generation is enabled. + /// + /// See Table 3-11 on page 3-14 for the parity truth table. + pub parity_enabled: bool, + /// BRK Send break. + /// + /// If this bit is set to `1`, a low-level is continually output o= n the + /// `UARTTXD` output, after completing transmission of the + /// current character. For the proper execution of the break comma= nd, + /// the software must set this bit for at least two complete + /// frames. For normal use, this bit must be cleared to `0`. + pub send_break: bool, + } + + impl LineControl { + pub fn reset(&mut self) { + // All the bits are cleared to 0 when reset. + *self =3D 0.into(); + } + } + + impl Default for LineControl { + fn default() -> Self { + 0.into() + } + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `EPS` "Even parity select", field of [Line Control + /// register](LineControl). + pub enum Parity { + /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of + /// 1s in the data and parity bits. + Odd =3D 0, + /// - 1 =3D even parity. The UART generates or checks for an even = number + /// of 1s in the data and parity bits. + Even =3D 1, + } + + #[bitsize(1)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control + /// register](LineControl). + pub enum Mode { + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers + Character =3D 0, + /// 1 =3D transmit and receive FIFO buffers are enabled (FIFO mode= ). + FIFO =3D 1, + } + + impl From for bool { + fn from(val: Mode) -> Self { + matches!(val, Mode::FIFO) + } + } + + #[bitsize(2)] + #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] + /// `WLEN` Word length, field of [Line Control register](LineControl). + /// + /// These bits indicate the number of data bits transmitted or receive= d in a + /// frame as follows: + pub enum WordLength { + /// b11 =3D 8 bits + _8Bits =3D 0b11, + /// b10 =3D 7 bits + _7Bits =3D 0b10, + /// b01 =3D 6 bits + _6Bits =3D 0b01, + /// b00 =3D 5 bits. + _5Bits =3D 0b00, + } + + /// Control Register, `UARTCR` + /// + /// The `UARTCR` register is the control register. All the bits are cl= eared + /// to `0` on reset except for bits `9` and `8` that are set to `1`. + /// + /// # Source + /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 + #[bitsize(16)] + #[doc(alias =3D "UARTCR")] + #[derive(Clone, Copy, DebugBits, FromBits)] + pub struct Control { + /// `UARTEN` UART enable: 0 =3D UART is disabled. If the UART is d= isabled + /// in the middle of transmission or reception, it completes the c= urrent + /// character before stopping. 1 =3D the UART is enabled. Data + /// transmission and reception occurs for either UART signals or S= IR + /// signals depending on the setting of the SIREN bit. + pub enable_uart: bool, + /// `SIREN` `SIR` enable: 0 =3D IrDA SIR ENDEC is disabled. `nSIRO= UT` + /// remains LOW (no light pulse generated), and signal transitions= on + /// SIRIN have no effect. 1 =3D IrDA SIR ENDEC is enabled. Data is + /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains= HIGH, + /// in the marking state. Signal transitions on UARTRXD or modem s= tatus + /// inputs have no effect. This bit has no effect if the UARTEN bit + /// disables the UART. + pub enable_sir: bool, + /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA enc= oding + /// mode. If this bit is cleared to 0, low-level bits are transmit= ted as + /// an active high pulse with a width of 3/ 16th of the bit period= . If + /// this bit is set to 1, low-level bits are transmitted with a pu= lse + /// width that is 3 times the period of the IrLPBaud16 input signa= l, + /// regardless of the selected bit rate. Setting this bit uses less + /// power, but might reduce transmission distances. + pub sir_lowpower_irda_mode: u1, + /// Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u4, + /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN b= it is + /// set to 1 and the SIRTEST bit in the Test Control register, UAR= TTCR + /// on page 4-5 is set to 1, then the nSIROUT path is inverted, an= d fed + /// through to the SIRIN path. The SIRTEST bit in the test registe= r must + /// be set to 1 to override the normal half-duplex SIR operation. = This + /// must be the requirement for accessing the test registers during + /// normal operation, and SIRTEST must be cleared to 0 when loopba= ck + /// testing is finished. This feature reduces the amount of extern= al + /// coupling required during system test. If this bit is set to 1,= and + /// the SIRTEST bit is set to 0, the UARTTXD path is fed through t= o the + /// UARTRXD path. In either SIR mode or UART mode, when this bit i= s set, + /// the modem outputs are also fed through to the modem inputs. Th= is bit + /// is cleared to 0 on reset, to disable loopback. + pub enable_loopback: bool, + /// `TXE` Transmit enable. If this bit is set to 1, the transmit s= ection + /// of the UART is enabled. Data transmission occurs for either UA= RT + /// signals, or SIR signals depending on the setting of the SIREN = bit. + /// When the UART is disabled in the middle of transmission, it + /// completes the current character before stopping. + pub enable_transmit: bool, + /// `RXE` Receive enable. If this bit is set to 1, the receive sec= tion + /// of the UART is enabled. Data reception occurs for either UART + /// signals or SIR signals depending on the setting of the SIREN b= it. + /// When the UART is disabled in the middle of reception, it compl= etes + /// the current character before stopping. + pub enable_receive: bool, + /// `DTR` Data transmit ready. This bit is the complement of the U= ART + /// data transmit ready, `nUARTDTR`, modem status output. That is,= when + /// the bit is programmed to a 1 then `nUARTDTR` is LOW. + pub data_transmit_ready: bool, + /// `RTS` Request to send. This bit is the complement of the UART + /// request to send, `nUARTRTS`, modem status output. That is, whe= n the + /// bit is programmed to a 1 then `nUARTRTS` is LOW. + pub request_to_send: bool, + /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1= `) + /// modem status output. That is, when the bit is programmed to a = 1 the + /// output is 0. For DTE this can be used as Data Carrier Detect (= DCD). + pub out_1: bool, + /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2= `) + /// modem status output. That is, when the bit is programmed to a = 1, the + /// output is 0. For DTE this can be used as Ring Indicator (RI). + pub out_2: bool, + /// `RTSEn` RTS hardware flow control enable. If this bit is set t= o 1, + /// RTS hardware flow control is enabled. Data is only requested w= hen + /// there is space in the receive FIFO for it to be received. + pub rts_hardware_flow_control_enable: bool, + /// `CTSEn` CTS hardware flow control enable. If this bit is set t= o 1, + /// CTS hardware flow control is enabled. Data is only transmitted= when + /// the `nUARTCTS` signal is asserted. + pub cts_hardware_flow_control_enable: bool, + } + + impl Control { + pub fn reset(&mut self) { + *self =3D 0.into(); + self.set_enable_receive(true); + self.set_enable_transmit(true); + } + } + + impl Default for Control { + fn default() -> Self { + let mut ret: Self =3D 0.into(); + ret.reset(); + ret + } + } + + /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC + pub const INT_OE: u32 =3D 1 << 10; + pub const INT_BE: u32 =3D 1 << 9; + pub const INT_PE: u32 =3D 1 << 8; + pub const INT_FE: u32 =3D 1 << 7; + pub const INT_RT: u32 =3D 1 << 6; + pub const INT_TX: u32 =3D 1 << 5; + pub const INT_RX: u32 =3D 1 << 4; + pub const INT_DSR: u32 =3D 1 << 3; + pub const INT_DCD: u32 =3D 1 << 2; + pub const INT_CTS: u32 =3D 1 << 1; + pub const INT_RI: u32 =3D 1 << 0; + pub const INT_E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const INT_MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + + #[repr(u32)] + pub enum Interrupt { + OE =3D 1 << 10, + BE =3D 1 << 9, + PE =3D 1 << 8, + FE =3D 1 << 7, + RT =3D 1 << 6, + TX =3D 1 << 5, + RX =3D 1 << 4, + DSR =3D 1 << 3, + DCD =3D 1 << 2, + CTS =3D 1 << 1, + RI =3D 1 << 0, + } + + impl Interrupt { + pub const E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; + pub const MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + } +} + +// TODO: You must disable the UART before any of the control registers are +// reprogrammed. When the UART is disabled in the middle of transmission or +// reception, it completes the current character before stopping diff --git a/rust/pl011/src/memory_ops.rs b/rust/pl011/src/memory_ops.rs new file mode 100644 index 0000000000..6144d28586 --- /dev/null +++ b/rust/pl011/src/memory_ops.rs @@ -0,0 +1,45 @@ +// Copyright 2024 Manos Pitsidianakis +// SPDX-License-Identifier: GPL-2.0 OR GPL-3.0-or-later + +use core::{mem::MaybeUninit, ptr::NonNull}; + +use qemu_api::bindings::*; + +use crate::device::PL011State; + +pub static PL011_OPS: MemoryRegionOps =3D MemoryRegionOps { + read: Some(pl011_read), + write: Some(pl011_write), + read_with_attrs: None, + write_with_attrs: None, + endianness: device_endian_DEVICE_NATIVE_ENDIAN, + valid: unsafe { MaybeUninit::::zeroed()= .assume_init() }, + impl_: MemoryRegionOps__bindgen_ty_2 { + min_access_size: 4, + max_access_size: 4, + ..unsafe { MaybeUninit::::zeroed().= assume_init() } + }, +}; + +#[no_mangle] +unsafe extern "C" fn pl011_read( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + size: core::ffi::c_uint, +) -> u64 { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().read(addr, size) +} + +#[no_mangle] +unsafe extern "C" fn pl011_write( + opaque: *mut core::ffi::c_void, + addr: hwaddr, + data: u64, + _size: core::ffi::c_uint, +) { + assert!(!opaque.is_null()); + let mut state =3D NonNull::new_unchecked(opaque.cast::()); + state.as_mut().write(addr, data) +} --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89