From nobody Sun Feb 23 11:33:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1740140983; cv=none; d=zohomail.com; s=zohoarc; b=mZ1+DXSKq7qCwJb7LwpzLL+457fxS/smQEHc0EyYeczmx6XPD45isXSPgjDLKheTiiCYbCHXZePlT4MiorcQXBldNPKKoC0T1Llpv/TvjrHCFfYUks8YGMZNTkAM0XvyBi2JeuXmWZWf99qKPse0zoNrS6vmO47Vk2a4UGVxzbE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740140983; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EBrAYudfN30eTDxsGlpkwQ5zRuzxrz1/bLUV220VFQI=; b=BZfo71oEdyX/0pMYqmwXD4qijOR/7ISc74+6w8AapP2PwVtIjdEVM6lF8V49oHKvse61ryftD5A3snF6WI3E4IR+mkzQpblhZdrPoAbKFtRvcm9g7bTIW4lKjaq/S1DZY9DwoqNzod1Z4KUW4y6efouW7CbomTMKpGdMZnk6ejI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740140983663732.9639642259841; Fri, 21 Feb 2025 04:29:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tlS5T-0002XN-HM; Fri, 21 Feb 2025 07:24:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tlS5O-000220-P3 for qemu-devel@nongnu.org; Fri, 21 Feb 2025 07:24:54 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tlS5M-0007Fd-QM for qemu-devel@nongnu.org; Fri, 21 Feb 2025 07:24:54 -0500 Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-9-DCDNizhyMLeCEixwv6WLRg-1; Fri, 21 Feb 2025 07:24:50 -0500 Received: by mail-wr1-f70.google.com with SMTP id ffacd0b85a97d-38f36fcf4b3so1229556f8f.1 for ; Fri, 21 Feb 2025 04:24:50 -0800 (PST) Received: from redhat.com ([31.187.78.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f259d65dfsm23693257f8f.64.2025.02.21.04.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 04:24:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1740140692; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=EBrAYudfN30eTDxsGlpkwQ5zRuzxrz1/bLUV220VFQI=; b=F2edohw3lZ3OM4n8gSLnfn1Dy8xsGniYwRIuLCUj+/H3dbqmdoxceCszA3P4jn1/AHk3zS kWShQea96gyHwO7hHgpX0n3A8S/CcsshLdcuLTH+PI3pMrkjm+oRMAtr2pyQUuLAS73NDv ZYZUcFkpg/K59C7B4N9Mm2/kgEEIkPE= X-MC-Unique: DCDNizhyMLeCEixwv6WLRg-1 X-Mimecast-MFC-AGG-ID: DCDNizhyMLeCEixwv6WLRg_1740140690 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740140689; x=1740745489; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=EBrAYudfN30eTDxsGlpkwQ5zRuzxrz1/bLUV220VFQI=; b=aT6WeTSA6b7ApHcSYFa8IGctDOMhrbxL1SuxvnNWcqIXbdz6Vbwe1p2nWgtAKABWqQ Mmi+Q/M+eEOl2YyOPo585PjBRPXSrxOozZBkiGs5iETHC3cWyMT/vKqKmcmWo7U9OyQt ASrrV4/GJLhL/CBLYzJQuACQkJPMzzmR7Ixu3ii6dyiv1qHBemgctaRasxQF7mYhE18j eodH52B1RuhKGPqVFqvNNz79wisMLbksKmBkUL2C0Qiu12vUU7dkb+9sa3Wt06ECFV0K 96RU+T2vUALtxXecuccVKUwpJgxUnW2XDCy+CO4ybD2ZWDYEsl+c+tnCrhjnDAGH2hLm thew== X-Gm-Message-State: AOJu0Yx69hy5yO94ieAuIDVq6Pi1JZKiN+t0M6NYpjujbXdCNy9/y0jg JPuQFVLZDrgdPacQ9dS4BsYzn1uKZRPZdOcxLyktQUU3+M3860Zrp+v60sHPVMlOTVsmf1tcJ4s CUU9gNE5DeRQLmCMSd2wzkyKu7Uyyil/tK0G3fdQ1Wu8R3CMvOhzMcub/7ZX+nofVjLDr2FITSA sJe1XujrmhjrG8ZGZUt8phJjvNqIu2aQ== X-Gm-Gg: ASbGncuzTs3/FD9ZiuPSH1kpy8Hc57jDs7bG1w6BRAMCsRsJwDvYD5Ny/8NXTXaBd/+ IJa0HyWCSafYNqd/ZTNgfeZsOTCNKK1g7XIwNxdoayA+sIW7ICjF4lLt05cuzFh3spKGz+/kcSF mXwONr/CIqO+5RLOW39rdsxbuJcRKlki+8Lm1OgXxneDXrczumRoIj5LKKsz0Yw4/4SbG6lA0V0 Q/3jklS7seNtRUfNK2xqIfrm+WnqKSCuY9AUe1Ci+INCfPuQBLYeli56Pr2T5Sr5eDmmsjTVf1V uRLtrw== X-Received: by 2002:a05:6000:178d:b0:38f:4263:9d62 with SMTP id ffacd0b85a97d-38f6e9791acmr2815549f8f.27.1740140689147; Fri, 21 Feb 2025 04:24:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IFp32AULRbmy01GSTfnKC2IjEC3TBFgsu2vbO9S8ZHJwsJenQ6kGgbMF8w2rfBY0Cmk08V9sg== X-Received: by 2002:a05:6000:178d:b0:38f:4263:9d62 with SMTP id ffacd0b85a97d-38f6e9791acmr2815517f8f.27.1740140688648; Fri, 21 Feb 2025 04:24:48 -0800 (PST) Date: Fri, 21 Feb 2025 07:24:45 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Eric Auger , Zhenzhong Duan , Peter Xu , qemu-arm@nongnu.org Subject: [PULL 39/41] hw/arm/smmuv3: Move reset to exit phase Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.424, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740140984336019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Eric Auger Currently the iommu may be reset before the devices it protects. For example this happens with virtio-scsi-pci. when system_reset is issued from qmp monitor: spurious "virtio: zero sized buffers are not allowed" warnings can be observed. This happens because outstanding DMA requests are still happening while the SMMU gets reset. This can also happen with VFIO devices. In that case spurious DMA translation faults can be observed on host. Make sure the SMMU is reset in the 'exit' phase after all DMA capable devices have been reset during the 'enter' or 'hold' phase. Signed-off-by: Eric Auger Reviewed-by: Zhenzhong Duan Message-Id: <20250218182737.76722-4-eric.auger@redhat.com> Reviewed-by: Peter Xu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/arm/smmu-common.c | 9 +++++++-- hw/arm/smmuv3.c | 14 ++++++++++---- hw/arm/trace-events | 1 + 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index dd74c2e558..8c1b407b82 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -924,7 +924,12 @@ static void smmu_base_realize(DeviceState *dev, Error = **errp) } } =20 -static void smmu_base_reset_hold(Object *obj, ResetType type) +/* + * Make sure the IOMMU is reset in 'exit' phase after + * all outstanding DMA requests have been quiesced during + * the 'enter' or 'hold' reset phases + */ +static void smmu_base_reset_exit(Object *obj, ResetType type) { SMMUState *s =3D ARM_SMMU(obj); =20 @@ -949,7 +954,7 @@ static void smmu_base_class_init(ObjectClass *klass, vo= id *data) device_class_set_props(dc, smmu_dev_properties); device_class_set_parent_realize(dc, smmu_base_realize, &sbc->parent_realize); - rc->phases.hold =3D smmu_base_reset_hold; + rc->phases.exit =3D smmu_base_reset_exit; } =20 static const TypeInfo smmu_base_info =3D { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c0cf5df0f6..b49a59b64c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1870,13 +1870,19 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDev= ice *dev) } } =20 -static void smmu_reset_hold(Object *obj, ResetType type) +/* + * Make sure the IOMMU is reset in 'exit' phase after + * all outstanding DMA requests have been quiesced during + * the 'enter' or 'hold' reset phases + */ +static void smmu_reset_exit(Object *obj, ResetType type) { SMMUv3State *s =3D ARM_SMMUV3(obj); SMMUv3Class *c =3D ARM_SMMUV3_GET_CLASS(s); =20 - if (c->parent_phases.hold) { - c->parent_phases.hold(obj, type); + trace_smmu_reset_exit(); + if (c->parent_phases.exit) { + c->parent_phases.exit(obj, type); } =20 smmuv3_init_regs(s); @@ -1999,7 +2005,7 @@ static void smmuv3_class_init(ObjectClass *klass, voi= d *data) SMMUv3Class *c =3D ARM_SMMUV3_CLASS(klass); =20 dc->vmsd =3D &vmstate_smmuv3; - resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL, + resettable_class_set_parent_phases(rc, NULL, NULL, smmu_reset_exit, &c->parent_phases); device_class_set_parent_realize(dc, smmu_realize, &c->parent_realize); diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c64ad344bd..7790db780e 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -56,6 +56,7 @@ smmuv3_config_cache_inv(uint32_t sid) "Config cache INV f= or sid=3D0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=3D%s asid=3D%d vm= id=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" stage=3D%d" +smmu_reset_exit(void) "" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 MST