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From: Roman Artemev <roman.artemev@syntacore.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
CC: "palmer@dabbelt.com" <palmer@dabbelt.com>, "Alistair.Francis@wdc.com"
<Alistair.Francis@wdc.com>, "richard.henderson@linaro.org"
<richard.henderson@linaro.org>, "qemu-riscv@nongnu.org"
<qemu-riscv@nongnu.org>, Roman Artemev <roman.artemev@syntacore.com>, "Denis
Tomashev" <denis.tomashev@syntacore.com>
Subject: [PATCH] tcg/riscv: Fix StoreStore barrier generation
Thread-Topic: [PATCH] tcg/riscv: Fix StoreStore barrier generation
Thread-Index: AQHbS5+XMPWvlhEe/kmr6ENsbls0/w==
Date: Wed, 11 Dec 2024 07:40:04 +0000
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On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index f8331e4688..96f9a7e348 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1624,7 +1624,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
insn |=3D 0x02100000;
}
if (a0 & TCG_MO_ST_ST) {
- insn |=3D 0x02200000;
+ insn |=3D 0x01100000;
}
tcg_out32(s, insn);
}
--=20
2.39.2