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X-Received-From: 68.232.143.124 Subject: [Qemu-devel] [PATCH v1 04/11] RISC-V: Allow interrupt controllers to claim interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) Content-Type: text/plain; charset="utf-8" From: Michael Clark We can't allow the supervisor to control SEIP as this would allow the supervisor to clear a pending external interrupt which will result in lost a interrupt in the case a PLIC is attached. The SEIP bit must be hardware controlled when a PLIC is attached. This logic was previously hard-coded so SEIP was always masked even if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts so that the PLIC can register control of SEIP. In the case of models without a PLIC (spike), the SEIP bit remains software controlled. This interface allows for hardware control of supervisor timer and software interrupts by other interrupt controller models. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Signed-off-by: Michael Clark Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 15 +++++++++++++++ target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 11 +++++++++++ target/riscv/csr.c | 10 ++-------- 4 files changed, 30 insertions(+), 8 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index b859f919a7..1c703e1a37 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -23,6 +23,7 @@ #include "qemu/error-report.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" +#include "sysemu/sysemu.h" #include "hw/riscv/sifive_plic.h" =20 #define RISCV_DEBUG_PLIC 0 @@ -431,6 +432,7 @@ static void sifive_plic_irq_request(void *opaque, int i= rq, int level) static void sifive_plic_realize(DeviceState *dev, Error **errp) { SiFivePLICState *plic =3D SIFIVE_PLIC(dev); + int i; =20 memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic, TYPE_SIFIVE_PLIC, plic->aperture_size); @@ -443,6 +445,19 @@ static void sifive_plic_realize(DeviceState *dev, Erro= r **errp) plic->enable =3D g_new0(uint32_t, plic->bitfield_words * plic->num_add= rs); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio); qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources); + + /* We can't allow the supervisor to control SEIP as this would allow t= he + * supervisor to clear a pending external interrupt which will result = in + * lost a interrupt in the case a PLIC is attached. The SEIP bit must = be + * hardware controlled when a PLIC is attached. + */ + for (i =3D 0; i < smp_cpus; i++) { + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(i)); + if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { + error_report("SEIP already claimed"); + exit(1); + } + } } =20 static void sifive_plic_class_init(ObjectClass *klass, void *data) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c2aebf132..a0b3c22dec 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -140,6 +140,7 @@ struct CPURISCVState { * mip is 32-bits to allow atomic_read on 32-bit hosts. */ uint32_t mip; + uint32_t miclaim; =20 target_ulong mie; target_ulong mideleg; @@ -263,6 +264,7 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprin= tf); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f49e98ed59..555756d40c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -72,6 +72,17 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 #if !defined(CONFIG_USER_ONLY) =20 +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) +{ + CPURISCVState *env =3D &cpu->env; + if (env->miclaim & interrupts) { + return -1; + } else { + env->miclaim |=3D interrupts; + return 0; + } +} + /* iothread_mutex must be held */ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 960d2b0aa9..938c10897c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -550,16 +550,10 @@ static int rmw_mip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { RISCVCPU *cpu =3D riscv_env_get_cpu(env); - target_ulong mask =3D write_mask & delegable_ints; + /* Allow software control of delegable interrupts not claimed by hardw= are */ + target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; =20 - /* We can't allow the supervisor to control SEIP as this would allow t= he - * supervisor to clear a pending external interrupt which will result = in - * lost a interrupt in the case a PLIC is attached. The SEIP bit must = be - * hardware controlled when a PLIC is attached. This should be an opti= on - * for CPUs with software-delegated Supervisor External Interrupts. */ - mask &=3D ~MIP_SEIP; - if (mask) { qemu_mutex_lock_iothread(); old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_value & mask)); --=20 2.20.1