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[37.6.163.245]) by smtp.gmail.com with ESMTPSA id cu3-20020a170906ba8300b00a3d014fa12esm3747876ejd.196.2024.02.20.00.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 00:53:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708419215; x=1709024015; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GDgHSGvtF7qGWqMyv82hrdTgzPdhn+1HJ5vS2mvdT+k=; b=WFs8ucruAXeC3ZWMKBzM8JO8YHKEN6OVm6dPuxfGoCggWu+h2kT4yNwRUx3+2ijAG5 HxNNCGy8XjlP9k34lYSla/pj6olcheJqfHpqEEZobRtJ1XRoyUy/HqYu+zqXi3MyqL13 Jsd3VONaZNZ0ZzdYRUFurXwXY44y7dLdPfUtXFbEjVZmFL7lelGyqTCAF6qfXtTw4NVJ mnccoNirNMYe5wMNcSPCO+lM4IIyoosGOKKeWISM1DH1Tw9wIXiTe9XaiqgSiONg7Ytl zIxJvFJLhPXsgdPF9wdWfZVlEWzN0hgKnegwjYEgj2qvrxpR7qs2avFe4hKKoF1Rro0g 42tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708419215; x=1709024015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GDgHSGvtF7qGWqMyv82hrdTgzPdhn+1HJ5vS2mvdT+k=; b=FrGtEFVZu8b4TWIud6Jxpx8bFEGs89btXaPowC/vTs+5bDjIFa12+VWFNeRE42h9xh zN27YNDsiQiKVfPqycvP5FIsZ4KkxHnlDh66eFWCuWwTI5b7WT8MBAJfeMzs7r77BcOY rrk2MvUmTFN0tJf3uBlkciLJfjwWxvqgkoUQ3T1Y9IRVO6HwLXsBdK4MhqIQSTEHix0O z/ov8qSSXVMpJTHZ+GS2/dIQANMbBn3gxD48ZppAZtftgxSPRVVX2UgbrbxEp1O93dJ5 bCiPYcaXZ9aGIwFA0GCbIOEnHzrNhFV61w9BRu33Ik0/vpzjmz5llDL3OntCgTZ+SQ7e lIGQ== X-Gm-Message-State: AOJu0YzgtebJxAB3y16AQa/f/NPPtNMl61kQRKZboSNJfsINzXXbHkbn irGTwWb0pmfVcNgsJZUQv7GUX+y0+FkSO0MI9G2/WX8kUORAKH8r5V8rrklA6+I= X-Google-Smtp-Source: AGHT+IF05Jr+3eODfG9nVaaMLbz71kgqZc91A+v3oTf+OAYzS9zC6++fOVnHWqwv1rRNXeKZHLqYuw== X-Received: by 2002:a17:907:100b:b0:a3e:876d:1b1 with SMTP id ox11-20020a170907100b00b00a3e876d01b1mr3944482ejb.20.1708419214949; Tue, 20 Feb 2024 00:53:34 -0800 (PST) From: Manos Pitsidianakis To: qemu-trivial@nongnu.org Cc: qemu-devel@nongnu.org, Michael Tokarev , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH v1 21/21] target/sparc: correct typos Date: Tue, 20 Feb 2024 10:52:28 +0200 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1708419325804100005 Content-Type: text/plain; charset="utf-8" Correct typos automatically found with the `typos` tool Signed-off-by: Manos Pitsidianakis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sparc/asi.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/sparc/asi.h b/target/sparc/asi.h index 3270ed0c7f..a66829674b 100644 --- a/target/sparc/asi.h +++ b/target/sparc/asi.h @@ -145,14 +145,14 @@ * and later ASIs. */ #define ASI_REAL 0x14 /* Real address, cacheable */ -#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */ -#define ASI_REAL_IO 0x15 /* Real address, non-cachable */ +#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */ +#define ASI_REAL_IO 0x15 /* Real address, non-cacheable */ #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ #define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */ #define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */ #define ASI_REAL_L 0x1c /* Real address, cacheable, LE */ -#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/ -#define ASI_REAL_IO_L 0x1d /* Real address, non-cachable, LE */ +#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cacheable, little endian*/ +#define ASI_REAL_IO_L 0x1d /* Real address, non-cacheable, LE */ #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ #define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/ #define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */ --=20 =CE=B3=CE=B1=E1=BF=96=CE=B1 =CF=80=CF=85=CF=81=CE=AF =CE=BC=CE=B9=CF=87=CE= =B8=CE=AE=CF=84=CF=89