From nobody Sat Feb 7 06:27:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547406307704264.9840102967306; Sun, 13 Jan 2019 11:05:07 -0800 (PST) Received: from localhost ([127.0.0.1]:39224 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gil4D-0004OZ-VT for importer@patchew.org; Sun, 13 Jan 2019 14:05:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:33313) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gil2l-0003aD-MQ for qemu-devel@nongnu.org; Sun, 13 Jan 2019 14:03:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gil2j-00045i-RB for qemu-devel@nongnu.org; Sun, 13 Jan 2019 14:03:35 -0500 Received: from pio-pvt-msa2.bahnhof.se ([79.136.2.41]:55302) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gil2j-00044Q-K9 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 14:03:33 -0500 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTP id 09AF63F534; Sun, 13 Jan 2019 20:03:26 +0100 (CET) Received: from pio-pvt-msa2.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa2.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Vx4CL8B_TGl2; Sun, 13 Jan 2019 20:03:21 +0100 (CET) Received: from localhost (h-41-252.A163.priv.bahnhof.se [46.59.41.252]) (Authenticated sender: mb547485) by pio-pvt-msa2.bahnhof.se (Postfix) with ESMTPA id CA0D33F39C; Sun, 13 Jan 2019 20:03:20 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at bahnhof.se Date: Sun, 13 Jan 2019 20:03:20 +0100 From: Fredrik Noring To: Aleksandar Markovic , Aurelien Jarno , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.41 Subject: [Qemu-devel] [PATCH 2/9] target/mips: Introduce 32 R5900 128-bit multimedia registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?Q?J=C3=BCrgen?= Urban , qemu-devel@nongnu.org, "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 32 R5900 128-bit MMRs are split into two 64-bit halves: the lower halves are the GPRs and the upper halves are accessible by the R5900- specific multimedia instructions. Signed-off-by: Fredrik Noring Reviewed-by: Aleksandar Markovic --- target/mips/cpu.h | 2 ++ target/mips/translate.c | 14 ++++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 03c03fd8c6..9ff4a68d90 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -180,6 +180,8 @@ struct TCState { #define MXU_CR_RD_EN 1 #define MXU_CR_MXU_EN 0 =20 + /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs= */ + uint64_t mmr[32]; }; =20 typedef struct CPUMIPSState CPUMIPSState; diff --git a/target/mips/translate.c b/target/mips/translate.c index a538351032..9d5150ec8b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2455,7 +2455,10 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; =20 -#if !defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) +/* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ +static TCGv_i64 cpu_mmr[32]; +#else /* MXU registers */ static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; static TCGv mxu_CR; @@ -29785,7 +29788,14 @@ void mips_tcg_init(void) fpu_fcr31 =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.f= cr31), "fcr31"); -#if !defined(TARGET_MIPS64) +#if defined(TARGET_MIPS64) + cpu_mmr[0] =3D NULL; + for (i =3D 1; i < 32; i++) + cpu_mmr[i] =3D tcg_global_mem_new_i64(cpu_env, + offsetof(CPUMIPSState, + active_tc.mmr[i]), + regnames[i]); +#else for (i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, --=20 2.19.2