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Thu, 4 Sep 2025 22:49:18 +0200 (CEST) Received: (qmail 2444 invoked by uid 990); 4 Sep 2025 20:49:18 -0000 Received: from unknown (HELO unkown) (::1) by skiff.uberspace.de (Haraka/3.0.1) with ESMTPSA; Thu, 04 Sep 2025 22:49:18 +0200 Authentication-Results: skiff.uberspace.de; auth=pass (plain) From: Julian Ganz To: qemu-devel@nongnu.org Cc: Julian Ganz , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v6 24/25] tests: add test for double-traps on rv64 Date: Thu, 4 Sep 2025 22:48:59 +0200 Message-ID: X-Mailer: git-send-email 2.49.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Bar: ----- X-Rspamd-Report: REPLY(-4) BAYES_HAM(-2.999521) MID_CONTAINS_FROM(1) MIME_GOOD(-0.1) R_MISSING_CHARSET(0.5) X-Rspamd-Score: -5.599521 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nut.email; s=uberspace; h=from:to:cc:subject:date; bh=hJeTNN+EDtHALUaN38ske2iZTHRjFTg++mevsB5iNj8=; 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helo=mailgate01.uberspace.is X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @nut.email) X-ZM-MESSAGEID: 1757019288336116600 Content-Type: text/plain; charset="utf-8" We do have a number of test-case for various architectures exercising their interrupt/exception logic. However, for the recently introduced trap API we also want to exercise the logic for double traps on at least one architecture. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Julian Ganz --- tests/tcg/riscv64/Makefile.softmmu-target | 6 ++ tests/tcg/riscv64/doubletrap.S | 73 +++++++++++++++++++++++ 2 files changed, 79 insertions(+) create mode 100644 tests/tcg/riscv64/doubletrap.S diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/= Makefile.softmmu-target index 3ca595335d..1a71a78653 100644 --- a/tests/tcg/riscv64/Makefile.softmmu-target +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -24,5 +24,11 @@ EXTRA_RUNS +=3D run-test-mepc-masking run-test-mepc-masking: test-mepc-masking $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<) =20 +EXTRA_RUNS +=3D run-plugin-doubletrap +run-plugin-doubletrap: doubletrap + $(call run-test, $<, \ + $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $*.pout \ + $(QEMU_OPTS)$<) + # We don't currently support the multiarch system tests undefine MULTIARCH_TESTS diff --git a/tests/tcg/riscv64/doubletrap.S b/tests/tcg/riscv64/doubletrap.S new file mode 100644 index 0000000000..b61089c9c1 --- /dev/null +++ b/tests/tcg/riscv64/doubletrap.S @@ -0,0 +1,73 @@ + .option norvc + + .text + .global _start +_start: + # Set up vectored interrupts + lla t0, trap + add t0, t0, 1 + csrw mtvec, t0 + + # Enable sw interrupts + csrrsi zero, mie, 0x8 + csrrsi zero, mstatus, 0x8 + + # Engage the double trap: we trigger an machine-level software + # interrupt, which will trap to an illegal instruction + lui t1, 0x02000 + li t0, 1 + sw t0, 0(t1) + + # If we still not went out via the software interrupt route after a + # short while, we failed the test. + lui t0, 0x1 +0: + addi t0, t0, -1 + bnez t0, 0b + j fail + +trap: + j illegal_insn # Exceptions + j fail # Supervisor software interrupt + j fail + .insn i CUSTOM_0, 0, x0, x0, 0 # Machine software interrupt + j fail + j fail # Supervisor timer interrupt + j fail + j fail # Machine timer interrupt + j fail + j fail # Supervisor external interrupt + j fail + j fail # Machine external interrupt + j fail + j fail # Counter overflow interrupt + j fail + j fail + +illegal_insn: + # Check whether we really got an illegal instruction + csrr t0, mcause + li t1, 2 + bne t0, t1, fail + li a0, 0 + j _exit +fail: + li a0, 1 +_exit: + lla a1, semiargs + li t0, 0x20026 # ADP_Stopped_ApplicationExit + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED + + # Semihosting call sequence + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 16 +semiargs: + .space 16 --=20 2.49.1