From nobody Wed Nov 19 13:56:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu ARC-Seal: i=1; a=rsa-sha256; t=1615944549; cv=none; d=zohomail.com; s=zohoarc; b=DS3dmwdL0bsnR+tPuKeWGMZP5jT07T72MU8qggGlFJcmOLeZOHEncromVCT7IeB6x3JJ3l7lNdmO+3nSzG5qpx6+pvLy2jr6LiEXs6Z7DvoVrPKtxvZ074qRDe6jKuMErVQfvK9uKGFbcsmgv8ZWKEvEKifsdFJwZDv0e5hOq9E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615944549; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8fL+rqhb5q9dPgh9nBTM7uQ+uJ0Tlt7iXR/Dlm2Iui8=; b=aBgxl+zMmTw/DsgtQMq028y0uwBKV6ETWDIhIN7bCjYxmwbEPtOZMXeWWsIM+iWQCDGS1Ca/2WTEXqgjU6CSzitpaxkQ+SHuq/Uk6hPmPGmzNLVyo6OghfohkyzyBDFEw9K5WQho/0MJ5QRAj2cV+Q+JyXpYORXuVxlFhtHF9Oo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615944549319723.5238998685621; Tue, 16 Mar 2021 18:29:09 -0700 (PDT) Received: from localhost ([::1]:36618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMKzk-0001Zl-98 for importer@patchew.org; Tue, 16 Mar 2021 21:29:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMKyc-0008Nb-Uz; Tue, 16 Mar 2021 21:27:58 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:55488) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMKyY-0000Sp-18; Tue, 16 Mar 2021 21:27:57 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id C7C7474641A; Wed, 17 Mar 2021 02:27:51 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 8AD1C7463AC; Wed, 17 Mar 2021 02:27:51 +0100 (CET) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v10 4/7] vt82c686: Add emulation of VT8231 south bridge Date: Wed, 17 Mar 2021 02:17:51 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Paolo Bonzini , f4bug@amsat.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Add emulation of VT8231 south bridge ISA part based on the similar VT82C686B but implemented in a separate subclass that holds the differences while reusing parts that can be shared. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/vt82c686.c | 84 +++++++++++++++++++++++++++++++++++++++ include/hw/isa/vt82c686.h | 1 + include/hw/pci/pci_ids.h | 1 + 3 files changed, 86 insertions(+) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 69f073ec9e..60a84d984b 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -8,6 +8,9 @@ * * Contributions after 2012-01-13 are licensed under the terms of the * GNU GPL, version 2 or (at your option) any later version. + * + * VT8231 south bridge support and general clean up to allow it + * Copyright (c) 2018-2020 BALATON Zoltan */ =20 #include "qemu/osdep.h" @@ -640,6 +643,86 @@ static const TypeInfo vt82c686b_isa_info =3D { .class_init =3D vt82c686b_class_init, }; =20 +/* TYPE_VT8231_ISA */ + +static void vt8231_write_config(PCIDevice *d, uint32_t addr, + uint32_t val, int len) +{ + ViaISAState *s =3D VIA_ISA(d); + + trace_via_isa_write(addr, val, len); + pci_default_write_config(d, addr, val, len); + if (addr =3D=3D 0x50) { + /* BIT(2): enable or disable superio config io ports */ + via_superio_io_enable(s->via_sio, val & BIT(2)); + } +} + +static void vt8231_isa_reset(DeviceState *dev) +{ + ViaISAState *s =3D VIA_ISA(dev); + uint8_t *pci_conf =3D s->dev.config; + + pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); + pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMO= RY | + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); + + pci_conf[0x58] =3D 0x40; /* Miscellaneous Control 0 */ + pci_conf[0x67] =3D 0x08; /* Fast IR Config */ + pci_conf[0x6b] =3D 0x01; /* Fast IR I/O Base */ +} + +static void vt8231_realize(PCIDevice *d, Error **errp) +{ + ViaISAState *s =3D VIA_ISA(d); + DeviceState *dev =3D DEVICE(d); + ISABus *isa_bus; + qemu_irq *isa_irq; + int i; + + qdev_init_gpio_out(dev, &s->cpu_intr, 1); + isa_irq =3D qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); + isa_bus =3D isa_bus_new(dev, get_system_memory(), pci_address_space_io= (d), + &error_fatal); + isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); + i8254_pit_init(isa_bus, 0x40, 0, NULL); + i8257_dma_init(isa_bus, 0); + s->via_sio =3D VIA_SUPERIO(isa_create_simple(isa_bus, TYPE_VT8231_SUPE= RIO)); + mc146818_rtc_init(isa_bus, 2000, NULL); + + for (i =3D 0; i < PCI_CONFIG_HEADER_SIZE; i++) { + if (i < PCI_COMMAND || i >=3D PCI_REVISION_ID) { + d->wmask[i] =3D 0; + } + } +} + +static void vt8231_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D vt8231_realize; + k->config_write =3D vt8231_write_config; + k->vendor_id =3D PCI_VENDOR_ID_VIA; + k->device_id =3D PCI_DEVICE_ID_VIA_8231_ISA; + k->class_id =3D PCI_CLASS_BRIDGE_ISA; + k->revision =3D 0x10; + dc->reset =3D vt8231_isa_reset; + dc->desc =3D "ISA bridge"; + dc->vmsd =3D &vmstate_via; + /* Reason: part of VIA VT8231 southbridge, needs to be wired up */ + dc->user_creatable =3D false; +} + +static const TypeInfo vt8231_isa_info =3D { + .name =3D TYPE_VT8231_ISA, + .parent =3D TYPE_VIA_ISA, + .instance_size =3D sizeof(ViaISAState), + .class_init =3D vt8231_class_init, +}; + =20 static void vt82c686b_register_types(void) { @@ -651,6 +734,7 @@ static void vt82c686b_register_types(void) type_register_static(&vt8231_superio_info); type_register_static(&via_isa_info); type_register_static(&vt82c686b_isa_info); + type_register_static(&vt8231_isa_info); } =20 type_init(vt82c686b_register_types) diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index 0692b9a527..0f01aaa471 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -3,6 +3,7 @@ =20 #define TYPE_VT82C686B_ISA "vt82c686b-isa" #define TYPE_VT82C686B_PM "vt82c686b-pm" +#define TYPE_VT8231_ISA "vt8231-isa" #define TYPE_VT8231_PM "vt8231-pm" #define TYPE_VIA_AC97 "via-ac97" #define TYPE_VIA_MC97 "via-mc97" diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index aa3f67eaa4..ac0c23ebc7 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -210,6 +210,7 @@ #define PCI_DEVICE_ID_VIA_82C686B_PM 0x3057 #define PCI_DEVICE_ID_VIA_AC97 0x3058 #define PCI_DEVICE_ID_VIA_MC97 0x3068 +#define PCI_DEVICE_ID_VIA_8231_ISA 0x8231 #define PCI_DEVICE_ID_VIA_8231_PM 0x8235 =20 #define PCI_VENDOR_ID_MARVELL 0x11ab --=20 2.21.4