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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775126911017154100 Content-Type: text/plain; charset="utf-8" Add HVX IEEE floating-point min/max instructions: - vfmin_hf, vfmin_sf: IEEE floating-point minimum - vfmax_hf, vfmax_sf: IEEE floating-point maximum - vmax_hf, vmax_sf: qfloat IEEE maximum - vmin_hf, vmin_sf: qfloat IEEE minimum The Hexagon qfloat variants are similar to the IEEE-754 ones, but they handle NaN slightly differently. See comment on hvx_ieee_fp.h Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/mmvec/hvx_ieee_fp.h | 12 ++++ target/hexagon/mmvec/hvx_ieee_fp.c | 62 ++++++++++++++++++++ target/hexagon/imported/mmvec/encode_ext.def | 10 ++++ target/hexagon/imported/mmvec/ext.idef | 36 +++++++++++- 4 files changed, 119 insertions(+), 1 deletion(-) diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index 5577179abd..f4801e3be9 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -44,4 +44,16 @@ uint32_t fp_vdmpy(uint16_t a1, uint16_t a2, uint16_t a3,= uint16_t a4, uint32_t fp_vdmpy_acc(uint32_t acc, uint16_t a1, uint16_t a2, uint16_t a3, uint16_t a4, float_status *fp_status); =20 +/* IEEE - FP min/max instructions */ +uint32_t fp_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status); +uint32_t fp_max_sf(uint32_t a1, uint32_t a2, float_status *fp_status); +uint16_t fp_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status); +uint16_t fp_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status); + +/* Qfloat min/max treat +NaN as greater than +INF and -NaN as smaller than= -INF */ +uint32_t qf_max_sf(uint32_t a1, uint32_t a2, float_status *fp_status); +uint32_t qf_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status); +uint16_t qf_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status); +uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status); + #endif diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c index ceb32ce43b..086e8dd29e 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.c +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -67,3 +67,65 @@ uint32_t fp_vdmpy_acc(uint32_t acc, uint16_t a1, uint16_= t a2, float32 red =3D fp_vdmpy(a1, a2, a3, a4, fp_status); return fp_add_sf_sf(float32_val(red), acc, fp_status); } + +DEF_FP_INSN_2(min_sf, 32, 32, 32, float32_min(f1, f2, fp_status)) +DEF_FP_INSN_2(max_sf, 32, 32, 32, float32_max(f1, f2, fp_status)) +DEF_FP_INSN_2(min_hf, 16, 16, 16, float16_min(f1, f2, fp_status)) +DEF_FP_INSN_2(max_hf, 16, 16, 16, float16_max(f1, f2, fp_status)) + +#define float32_is_pos_nan(X) (float32_is_any_nan(X) && !float32_is_neg(X)) +#define float32_is_neg_nan(X) (float32_is_any_nan(X) && float32_is_neg(X)) +#define float16_is_pos_nan(X) (float16_is_any_nan(X) && !float16_is_neg(X)) +#define float16_is_neg_nan(X) (float16_is_any_nan(X) && float16_is_neg(X)) + +uint32_t qf_max_sf(uint32_t a1, uint32_t a2, float_status *fp_status) +{ + float32 f1 =3D make_float32(a1); + float32 f2 =3D make_float32(a2); + if (float32_is_pos_nan(f1) || float32_is_neg_nan(f2)) { + return a1; + } + if (float32_is_pos_nan(f2) || float32_is_neg_nan(f1)) { + return a2; + } + return fp_max_sf(a1, a2, fp_status); +} + +uint32_t qf_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status) +{ + float32 f1 =3D make_float32(a1); + float32 f2 =3D make_float32(a2); + if (float32_is_pos_nan(f1) || float32_is_neg_nan(f2)) { + return a2; + } + if (float32_is_pos_nan(f2) || float32_is_neg_nan(f1)) { + return a1; + } + return fp_min_sf(a1, a2, fp_status); +} + +uint16_t qf_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status) +{ + float16 f1 =3D make_float16(a1); + float16 f2 =3D make_float16(a2); + if (float16_is_pos_nan(f1) || float16_is_neg_nan(f2)) { + return a1; + } + if (float16_is_pos_nan(f2) || float16_is_neg_nan(f1)) { + return a2; + } + return fp_max_hf(a1, a2, fp_status); +} + +uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status) +{ + float16 f1 =3D make_float16(a1); + float16 f2 =3D make_float16(a2); + if (float16_is_pos_nan(f1) || float16_is_neg_nan(f2)) { + return a2; + } + if (float16_is_pos_nan(f2) || float16_is_neg_nan(f1)) { + return a1; + } + return fp_min_hf(a1, a2, fp_status); +} diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 4ce87d09fd..d7f50db778 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -823,4 +823,14 @@ DEF_ENC(V6_vsub_sf_hf,"00011111100vvvvvPP1uuuuu101dddd= d") DEF_ENC(V6_vadd_hf_hf,"00011111101vvvvvPP1uuuuu111ddddd") DEF_ENC(V6_vsub_hf_hf,"00011111011vvvvvPP1uuuuu000ddddd") =20 +/* IEEE FP min/max instructions */ +DEF_ENC(V6_vfmin_hf,"00011100011vvvvvPP1uuuuu000ddddd") +DEF_ENC(V6_vfmin_sf,"00011100011vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vfmax_hf,"00011100011vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vfmax_sf,"00011100011vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vmax_sf,"00011111110vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vmin_sf,"00011111110vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vmax_hf,"00011111110vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vmin_hf,"00011111110vvvvvPP1uuuuu100ddddd") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index e800cda317..19135853d4 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -43,7 +43,9 @@ EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA), \ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 - +#define ITERATOR_INSN_ANY_SLOT_2SRC(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC= ,A_HVX_FLT), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 #define ITERATOR_INSN2_ANY_SLOT(WIDTH,TAG,SYNTAX,SYNTAX2,DESCR,CODE) \ ITERATOR_INSN_ANY_SLOT(WIDTH,TAG,SYNTAX2,DESCR,CODE) @@ -2992,6 +2994,38 @@ ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_hf, VddV.v[0].sf[i] =3D fp_sub_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_f= p_status); VddV.v[1].sf[i] =3D fp_sub_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->h= vx_fp_status)) =20 +#define ITERATOR_INSN_IEEE_FP_16_32_LATE(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ + ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT= _16,A_HVX_IEEE_FP_OUT_32), \ + DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* IEEE FP min/max instructions */ +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmin_hf, "Vd32.hf=3Dvfmin(Vu32.hf,Vv= 32.hf)", \ + "Vector IEEE min: hf", VdV.hf[i] =3D fp_min_hf(VuV.hf[i], VvV.hf[i], \ + &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmin_sf, "Vd32.sf=3Dvfmin(Vu32.sf,Vv= 32.sf)", \ + "Vector IEEE min: sf", VdV.sf[i] =3D fp_min_sf(VuV.sf[i], VvV.sf[i], \ + &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmax_hf, "Vd32.hf=3Dvfmax(Vu32.hf,V= v32.hf)", \ + "Vector IEEE max: hf", VdV.hf[i] =3D fp_max_hf(VuV.hf[i], VvV.hf[i], \ + &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmax_sf, "Vd32.sf=3Dvfmax(Vu32.sf,V= v32.sf)", \ + "Vector IEEE max: sf", VdV.sf[i] =3D fp_max_sf(VuV.sf[i], VvV.sf[i], \ + &env->hvx_fp_status)) + +ITERATOR_INSN_ANY_SLOT_2SRC(32,vmax_sf,"Vd32.sf=3Dvmax(Vu32.sf,Vv32.sf)", \ + "Vector max of sf input", VdV.sf[i] =3D qf_max_sf(VuV.sf[i], VvV.sf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_ANY_SLOT_2SRC(32,vmin_sf,"Vd32.sf=3Dvmin(Vu32.sf,Vv32.sf)", \ + "Vector min of sf input", VdV.sf[i] =3D qf_min_sf(VuV.sf[i], VvV.sf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_ANY_SLOT_2SRC(16,vmax_hf,"Vd32.hf=3Dvmax(Vu32.hf,Vv32.hf)", \ + "Vector max of hf input", VdV.hf[i] =3D qf_max_hf(VuV.hf[i], VvV.hf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,"Vd32.hf=3Dvmin(Vu32.hf,Vv32.hf)", \ + "Vector min of hf input", VdV.hf[i] =3D qf_min_hf(VuV.hf[i], VvV.hf[i]= , \ + &env->hvx_fp_status)) + /*************************************************************************= ***** DEBUG Vector/Register Printing *************************************************************************= *****/ --=20 2.37.2