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X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eeb3756c91..b99d2b7af2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -169,12 +169,29 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + /* Hypervisor CSRs */ + target_ulong hstatus; + target_ulong hedeleg; + target_ulong hideleg; + target_ulong hgatp; + target_ulong scounteren; target_ulong mcounteren; =20 target_ulong sscratch; target_ulong mscratch; =20 + /* Background CSRs */ + target_ulong bsstatus; + target_ulong bsip; + target_ulong bsie; + target_ulong bstvec; + target_ulong bsscratch; + target_ulong bsepc; + target_ulong bscause; + target_ulong bstval; + target_ulong bsatp; + /* temporary htif regs */ uint64_t mfromhost; uint64_t mtohost; --=20 2.21.0