From nobody Sat Oct 24 00:32:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=sloservers.com ARC-Seal: i=1; a=rsa-sha256; t=1790948933; cv=none; d=zohomail.com; s=zohoarc; b=eFwiulLsut0ScmpfaXmCgg28vvFEkhkI4Qlx751LWsV31UfA1QQHJW5eSvjOOemzWZUu/1bFv7YqI0IaOdIG23kWuGIOrWcY4J0G4AomAA4fwlAzZZqWYd1ARwL+3wuoclAcZ+R+6dr14AqErix2mOX/MJ3PLymLP4HKJxQ8y9o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790948933; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=X/rAufdl4WUacev28wGy7SGRE3Ug56V0VeC3fOx+6Ws=; b=XrDHK2loFGUfCuqLRAr5HMYJ565lP+Mpbj7aZJX4EyjUkKEAnvyNfPQKNJ8ItTMY0rgDZ6g+5gfPZuZg4Xd3RId5R4uMiutS3aoyWF4Bu51j8HBmctiCcm0TD3NLvrzLm3H4mYM1lhX5r0MZ1OTUGSrIGXvbtP+KEBAiwkeDe6g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790948933104788.9693520934982; Fri, 2 Oct 2026 06:48:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xCdcQ-0000HX-6a; Fri, 02 Oct 2026 09:48:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCdcN-0000HJ-7O; Fri, 02 Oct 2026 09:48:07 -0400 Received: from vps.sloservers.com ([204.109.61.218]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xCdcJ-000698-8i; Fri, 02 Oct 2026 09:48:05 -0400 Received: from thinking.duckdns.org (unknown [192.168.11.4]) by vps.sloservers.com (Postfix) with ESMTPS id F404223ABD; Fri, 02 Oct 2026 13:48:00 +0000 (UTC) Received: from [192.168.1.131] (OPNsense.thinking.duckdns.org [192.168.1.5]) by thinking.duckdns.org (Postfix) with ESMTPSA id 55135C5F; Fri, 02 Oct 2026 06:48:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sloservers.com; s=mail; t=1790948881; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=X/rAufdl4WUacev28wGy7SGRE3Ug56V0VeC3fOx+6Ws=; b=IheFvqDcNKKZifAoIXF4AsI2NhBXSiQ+rkfhcoiiI73WbVe03Q4dbPmYs4JwprsE9EMFjB IIs942asGxKosyG6z56YG3aOaRop7rex0KR1mvPllnj+CTcj+3kyAAAjSscOrADu0O4Zl9 cbrqAYXdj8OWYKPxMMPrWAZ0OYIYz50ebWpWrq2pfMtTWh8OlGzz9BQJnXCJl3HM3fecjd KCJqIfMFiyj5zSzRcdJfjtEwZFsVBjVIun+mT/krGX1YvDoP5yyQKg83nWnqZYlVs+sKfn 1CBZ3xTfIqyp/TS2cyFkGuuogiFibztGXMQ/aW5xb0u8Rszm3C+Y39PVm15pKA== Message-ID: Date: Fri, 2 Oct 2026 06:47:58 -0700 MIME-Version: 1.0 User-Agent: Betterbird (Windows) Content-Language: en-US To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com From: Rick Richard Subject: [PATCH] target/riscv: Use TSO barriers instead of full barriers for Ztso Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=204.109.61.218; envelope-from=rick@sloservers.com; helo=vps.sloservers.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sloservers.com) X-ZM-MESSAGEID: 1790948936730158500 Content-Type: text/plain; charset="utf-8" With Ztso, plain loads and stores follow RVTSO, but the barriers around them use TCG_MO_ALL. That also orders a store before a later load, which TSO doesn't require, and is expensive: on x86 hosts it adds a locked instruction around every load and store in a multi-threaded guest. The barrier after a load now only keeps later loads and stores behind it, and the barrier before a store only keeps earlier loads and stores ahead of it. That is all TSO needs. Signed-off-by: Rick Richard Reviewed-by: Daniel Henrique Barboza Reviewed-by: Palmer Dabbelt --- I found this while looking into why riscv64 guests were so much slower than aarch64 ones under bsd-user on FreeBSD. The default -cpu max enables Ztso, and turning it off with ztso=3Dfalse accounted for most of the difference. On an x86-64 host the patch made xz almost four times faster and cut the time of a clang compile by about 30%, the same as running with ztso=3Dfalse. The output didn't change. I also tested it on a Raspberry Pi 3B+, which is arm64 and doesn't give TSO ordering in hardware, to make sure the weaker barriers still hold up there. Everything ran correctly, and xz was about 12% faster. target/riscv/tcg/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/tcg/insn_trans/trans_rvv.c.inc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/insn_trans/trans_rvi.c.inc b/target/riscv/tcg= /insn_trans/trans_rvi.c.inc index 40b4c9aa..d31e4295 100644 --- a/target/riscv/tcg/insn_trans/trans_rvi.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvi.c.inc @@ -424,7 +424,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) } =20 if (ctx->ztso) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + tcg_gen_mb(TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_BAR_LDAQ); } =20 return out; @@ -485,7 +485,7 @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a, = MemOp memop) TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 if (ctx->ztso) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + tcg_gen_mb(TCG_MO_LD_ST | TCG_MO_ST_ST | TCG_BAR_STRL); } =20 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg= /insn_trans/trans_rvv.c.inc index a22e2cae..8c21ab87 100644 --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc @@ -731,7 +731,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, * around the loop. */ if (is_store && s->ztso) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + tcg_gen_mb(TCG_MO_LD_ST | TCG_MO_ST_ST | TCG_BAR_STRL); } =20 mark_vs_dirty(s); @@ -739,7 +739,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, fn(dest, mask, base, tcg_env, desc); =20 if (!is_store && s->ztso) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + tcg_gen_mb(TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_BAR_LDAQ); } =20 finalize_rvv_inst(s); --=20 2.43.0