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Thu, 02 Apr 2026 03:47:47 -0700 (PDT) X-Received: by 2002:a05:7300:fd0b:b0:2c1:14ca:7c86 with SMTP id 5a478bee46e88-2c932db3e06mr3601605eec.32.1775126866527; Thu, 02 Apr 2026 03:47:46 -0700 (PDT) From: Matheus Tavares Bernardino To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng, brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com Subject: [PATCH v2 11/16] target/hexagon: add v73 HVX IEEE bfloat16 insns Date: Thu, 2 Apr 2026 03:47:28 -0700 Message-Id: X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=TqLrRTXh c=1 sm=1 tr=0 ts=69ce4954 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=mMeFUOTstzKuDvyCm9AA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: BTJGmrKy-wtWZ9NFhMDAmNN_F0EG28fP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAyMDA5NyBTYWx0ZWRfXyCGXoNZUeZxO BA2hlR7Af2e2KM26udsSzhU9yW0tQOqTdIVoMQmSBpNACEI3wrfgHQdkif//I7DlzkNrGHd1oC6 pxTya5aBuTTuFRFWua89muPlD4kuBHXD78lG14lRX0DmiUETr1sWdS89+gZSoYAz0W0JMm94nM9 lmlvWavieaJLxC+JfpTJCx2WOvmbpoP1ZBkKKge/HknOPqvhSmPqiOrvxsML5IQ+fRY8QjqbwOE bTnr5YqbDsG8AkmVfXltV+vpxQOrgCrBiAm1XiopdtUgZW30Oyf+M36hiPrbW2aVU53rDl9zlk8 hWBR+wt/irQT1VQPHn/YpaY/jb48i7prduuY26JqMRUfQqpv62Fcao9WpYWjtjGaF2e50uTHO9Z O6Xy7GD5BK++BpFA/dd1Yymm4v5/I02ltYAsNpD6uO6U8uz9qJuh1KB/6bBg1V6EUopuCEdhO6n gSdBb4PVq+8mrkc+D9A== X-Proofpoint-GUID: BTJGmrKy-wtWZ9NFhMDAmNN_F0EG28fP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-02_01,2026-04-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 spamscore=0 adultscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604020097 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775126936105158500 Content-Type: text/plain; charset="utf-8" Add HVX IEEE bfloat16 (bf16) instructions: Arithmetic operations: - V6_vadd_sf_bf, V6_vsub_sf_bf: add/sub bf16 widening to sf output - V6_vmpy_sf_bf: multiply bf16 widening to sf output - V6_vmpy_sf_bf_acc: multiply-accumulate bf16 widening to sf output Min/Max operations: - V6_vmin_bf, V6_vmax_bf: bf16 min/max Comparison operations: - V6_vgtbf: greater-than compare - V6_vgtbf_and, V6_vgtbf_or, V6_vgtbf_xor: predicate variants Conversion operations: - V6_vcvt_bf_sf: convert sf to bf16 Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/mmvec/hvx_ieee_fp.h | 44 ++++++++++++++ target/hexagon/mmvec/macros.h | 4 ++ target/hexagon/mmvec/mmvec.h | 1 + target/hexagon/mmvec/hvx_ieee_fp.c | 4 ++ target/hexagon/imported/mmvec/encode_ext.def | 15 +++++ target/hexagon/imported/mmvec/ext.idef | 64 ++++++++++++++++++++ 6 files changed, 132 insertions(+) diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index b68d6db23e..0ca529b627 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -81,4 +81,48 @@ int16_t conv_hf_h(int16_t a, float_status *fp_status); int32_t conv_w_sf(uint32_t a, float_status *fp_status); int16_t conv_h_hf(uint16_t a, float_status *fp_status); =20 +/* IEEE BFloat instructions */ + +#define fp_mult_sf_bf(A, B) \ + fp_mult_sf_sf(bfloat16_to_float32(A, &env->hvx_fp_status), \ + bfloat16_to_float32(B, &env->hvx_fp_status), \ + &env->hvx_fp_status) +#define fp_add_sf_bf(A, B) \ + fp_add_sf_sf(bfloat16_to_float32(A, &env->hvx_fp_status), \ + bfloat16_to_float32(B, &env->hvx_fp_status), \ + &env->hvx_fp_status) +#define fp_sub_sf_bf(A, B) \ + fp_sub_sf_sf(bfloat16_to_float32(A, &env->hvx_fp_status), \ + bfloat16_to_float32(B, &env->hvx_fp_status), \ + &env->hvx_fp_status) + +uint32_t fp_mult_sf_bf_acc(uint16_t op1, uint16_t op2, uint32_t acc, + float_status *fp_status); + +#define bf_to_sf(A, fp_status) bfloat16_to_float32(A, fp_status) + +static inline uint16_t sf_to_bf(int32_t A, float_status *fp_status) +{ + uint32_t rslt =3D A; + if ((rslt & 0x1FFFF) =3D=3D 0x08000) { + /* do not round up if exactly .5 and even already */ + } else if ((rslt & 0x8000) =3D=3D 0x8000) { + rslt +=3D 0x8000; /* rounding to nearest number */ + } + rslt =3D float32_is_any_nan(A) ? FP32_DEF_NAN : rslt; + return float32_to_bfloat16(rslt, fp_status); +} + +#define fp_min_bf(A, B) \ + sf_to_bf(fp_min_sf(bf_to_sf(A, &env->hvx_fp_status), \ + bf_to_sf(B, &env->hvx_fp_status), \ + &env->hvx_fp_status), \ + &env->hvx_fp_status); + +#define fp_max_bf(A, B) \ + sf_to_bf(fp_max_sf(bf_to_sf(A, &env->hvx_fp_status), \ + bf_to_sf(B, &env->hvx_fp_status), \ + &env->hvx_fp_status), \ + &env->hvx_fp_status); + #endif diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 318d44efb7..4945a61194 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -25,6 +25,9 @@ #include "accel/tcg/probe.h" #include "mmvec/hvx_ieee_fp.h" =20 +#define fBFLOAT() +#define fCVI_VX_NO_TMP_LD() + #ifndef QEMU_GENERATE #define VdV (*(MMVector *restrict)(VdV_void)) #define VsV (*(MMVector *restrict)(VsV_void)) @@ -358,5 +361,6 @@ =20 #define fCMPGT_SF(A, B) cmpgt_sf(A, B, &env->hvx_fp_status) #define fCMPGT_HF(A, B) cmpgt_hf(A, B, &env->hvx_fp_status) +#define fCMPGT_BF(A, B) fCMPGT_SF((uint32_t)(A) << 16, (uint32_t)(B) << 16) =20 #endif diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h index eaedfe0d6d..9d8d57c7c6 100644 --- a/target/hexagon/mmvec/mmvec.h +++ b/target/hexagon/mmvec/mmvec.h @@ -40,6 +40,7 @@ typedef union { int8_t b[MAX_VEC_SIZE_BYTES / 1]; int32_t sf[MAX_VEC_SIZE_BYTES / 4]; /* single float (32-bit) */ int16_t hf[MAX_VEC_SIZE_BYTES / 2]; /* half float (16-bit) */ + uint16_t bf[MAX_VEC_SIZE_BYTES / 2]; /* bfloat16 */ } MMVector; =20 typedef union { diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c index 131d8e5595..9e2cff2ef7 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.c +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -269,3 +269,7 @@ uint16_t cmpgt_hf(uint16_t a1, uint16_t a2, float_statu= s *fp_status) } return float16_compare(a1, a2, fp_status) =3D=3D float_relation_greate= r; } + +DEF_FP_INSN_3(mult_sf_bf_acc, 32, 16, 16, 32, + float32_muladd(bf_to_sf(f1, fp_status), bf_to_sf(f2, fp_stat= us), + f3, 0, fp_status)) diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 3572e4de4c..16f043b77d 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -868,4 +868,19 @@ DEF_ENC(V6_vgthf_or,"00011100100vvvvvPP1uuuuu001101xx") DEF_ENC(V6_vgtsf_xor,"00011100100vvvvvPP1uuuuu111010xx") DEF_ENC(V6_vgthf_xor,"00011100100vvvvvPP1uuuuu111011xx") =20 +/* BFLOAT instructions */ +DEF_ENC(V6_vmpy_sf_bf,"00011101010vvvvvPP1uuuuu100ddddd") +DEF_ENC(V6_vmpy_sf_bf_acc,"00011101000vvvvvPP1uuuuu000xxxxx") +DEF_ENC(V6_vadd_sf_bf,"00011101010vvvvvPP1uuuuu110ddddd") +DEF_ENC(V6_vsub_sf_bf,"00011101010vvvvvPP1uuuuu101ddddd") +DEF_ENC(V6_vmax_bf,"00011101010vvvvvPP1uuuuu111ddddd") +DEF_ENC(V6_vmin_bf,"00011101010vvvvvPP1uuuuu000ddddd") +DEF_ENC(V6_vcvt_bf_sf,"00011101010vvvvvPP1uuuuu011ddddd") + +/* BFLOAT compare instructions */ +DEF_ENC(V6_vgtbf,"00011100100vvvvvPP1uuuuu011110dd") +DEF_ENC(V6_vgtbf_and,"00011100100vvvvvPP1uuuuu110100xx") +DEF_ENC(V6_vgtbf_or,"00011100100vvvvvPP1uuuuu001110xx") +DEF_ENC(V6_vgtbf_xor,"00011100100vvvvvPP1uuuuu111100xx") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 6f01a9d48f..aaae2d90e1 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -3155,6 +3155,15 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,"Vd32.hf= =3DVu32.h", } \ } =20 +#define VCMPGT_BF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \ +{ \ + fBFLOAT(); \ + for (fHIDE(int) i =3D 0; i < fVBYTES(); i +=3D WIDTH) { \ + fHIDE(int) VAL =3D fCMPGT_BF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? = MASK : 0; \ + fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \ + } \ +} + /* Vector SF compare */ #define MMVEC_CMPGT_SF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \ EXTINSN(V6_vgt##TYPE##_and, "Qx4&=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ @@ -3193,8 +3202,63 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,"Vd32.hf= =3DVu32.h", DESCR" greater than", \ VCMPGT_HF(QdV, , , ">", N, SRC, MASK, WIDTH)) =20 +/* Vector BF compare */ +#define MMVEC_CMPGT_BF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \ + EXTINSN(V6_vgt##TYPE##_and, "Qx4&=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")",\ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-and", \ + VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE##_xor, "Qx4^=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE= 2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-xor", \ + VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE##_or, "Qx4|=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE2= ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than with predicate-or", \ + VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, ">", N, SRC, MASK, = WIDTH)) \ + EXTINSN(V6_vgt##TYPE, "Qd4=3Dvcmp.gt(Vu32." TYPE2 ",Vv32." TYPE2 ")", \ + ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \ + DESCR" greater than", \ + VCMPGT_BF(QdV, , , ">", N, SRC, MASK, WIDTH)) + MMVEC_CMPGT_SF(sf,"sf","Vector sf Compare ", fVELEM(32), 0xF, 4, sf) MMVEC_CMPGT_HF(hf,"hf","Vector hf Compare ", fVELEM(16), 0x3, 2, hf) +MMVEC_CMPGT_BF(bf,"bf","Vector bf Compare ", fVELEM(16), 0x3, 2, bf) + +/*************************************************************************= ***** + BFloat arithmetic and max/min instructions + *************************************************************************= *****/ + +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vadd_sf_bf, + "Vdd32.sf=3Dvadd(Vu32.bf,Vv32.bf)", "Vector IEEE add: bf widen to sf", + VddV.v[0].sf[i] =3D fp_add_sf_bf(VuV.bf[2*i], VvV.bf[2*i]); + VddV.v[1].sf[i] =3D fp_add_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOA= T()) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_bf, + "Vdd32.sf=3Dvsub(Vu32.bf,Vv32.bf)", "Vector IEEE sub: bf widen to sf", + VddV.v[0].sf[i] =3D fp_sub_sf_bf(VuV.bf[2*i], VvV.bf[2*i]); + VddV.v[1].sf[i] =3D fp_sub_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOA= T()) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_bf, + "Vdd32.sf=3Dvmpy(Vu32.bf,Vv32.bf)", "Vector IEEE mul: hf widen to sf", + VddV.v[0].sf[i] =3D fp_mult_sf_bf(VuV.bf[2*i], VvV.bf[2*i]); + VddV.v[1].sf[i] =3D fp_mult_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLO= AT()) +ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_bf_acc, + "Vxx32.sf+=3Dvmpy(Vu32.bf,Vv32.bf)", "Vector IEEE fma: hf widen to sf", + VxxV.v[0].sf[i] =3D fp_mult_sf_bf_acc(VuV.bf[2*i], VvV.bf[2*i], + VxxV.v[0].sf[i], &env->hvx_fp_stat= us); + VxxV.v[1].sf[i] =3D fp_mult_sf_bf_acc(VuV.bf[2*i+1], VvV.bf[2*i+1], + VxxV.v[1].sf[i], &env->hvx_fp_stat= us); + fCVI_VX_NO_TMP_LD(); fBFLOAT()) +ITERATOR_INSN_IEEE_FP_16(32, vcvt_bf_sf, + "Vd32.bf=3Dvcvt(Vu32.sf,Vv32.sf)", "Vector IEEE cvt: sf to bf", + VdV.bf[2*i] =3D sf_to_bf(VuV.sf[i], &env->hvx_fp_status); + VdV.bf[2*i+1] =3D sf_to_bf(VvV.sf[i], &env->hvx_fp_status); fBFLOAT()) + +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmax_bf, "Vd32.bf=3Dvmax(Vu32.bf,Vv32= .bf)", + "Vector IEEE max: bf", VdV.bf[i] =3D fp_max_bf(VuV.bf[i], VvV.bf[i]); + fBFLOAT()) +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmin_bf, "Vd32.bf=3Dvmin(Vu32.bf,Vv32= .bf)", + "Vector IEEE max: bf", VdV.bf[i] =3D fp_min_bf(VuV.bf[i], VvV.bf[i]); + fBFLOAT()) =20 /*************************************************************************= ***** DEBUG Vector/Register Printing --=20 2.37.2