From nobody Thu Dec 18 04:30:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1540137001251431.27495274813646; Sun, 21 Oct 2018 08:50:01 -0700 (PDT) Received: from localhost ([::1]:59341 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEFzM-0005Vp-1t for importer@patchew.org; Sun, 21 Oct 2018 11:50:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46190) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEFok-0004Ef-Vs for qemu-devel@nongnu.org; Sun, 21 Oct 2018 11:39:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEFog-00041H-Su for qemu-devel@nongnu.org; Sun, 21 Oct 2018 11:39:02 -0400 Received: from pio-pvt-msa1.bahnhof.se ([79.136.2.40]:35113) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gEFof-00040D-Ai for qemu-devel@nongnu.org; Sun, 21 Oct 2018 11:38:58 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTP id 0E7603F486; Sun, 21 Oct 2018 17:38:51 +0200 (CEST) Received: from pio-pvt-msa1.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa1.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id scqaaIwGsdN0; Sun, 21 Oct 2018 17:38:50 +0200 (CEST) Received: from localhost (h-41-252.A163.priv.bahnhof.se [46.59.41.252]) (Authenticated sender: mb547485) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTPA id D5F1E3F3A9; Sun, 21 Oct 2018 17:38:49 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se Date: Sun, 21 Oct 2018 17:38:49 +0200 From: Fredrik Noring To: Aleksandar Markovic , "Maciej W. Rozycki" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.40 Subject: [Qemu-devel] [PATCH v8 19/38] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-devel@nongnu.org, =?utf-8?Q?J=C3=BCrgen?= Urban , Petar Jovanovic , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Fredrik Noring --- disas/mips.c | 4 ++++ target/mips/translate.c | 23 +++++++++++++++++------ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/disas/mips.c b/disas/mips.c index ae72059c46..e86a2b8764 100644 --- a/disas/mips.c +++ b/disas/mips.c @@ -2594,8 +2594,10 @@ const struct mips_opcode mips_builtin_opcodes[] =3D {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, +{"mfhi1", "d", 0x70000010, 0xffff07ff, WR_d|RD_HI, 0,= EE }, {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, +{"mflo1", "d", 0x70000012, 0xffff07ff, WR_d|RD_LO, 0,= EE }, {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|S= B1 }, {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, @@ -2661,8 +2663,10 @@ const struct mips_opcode mips_builtin_opcodes[] =3D {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, +{"mthi1", "s", 0x70000011, 0xfc1fffff, RD_s|WR_HI, 0,= EE }, {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, +{"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_s|WR_LO, 0,= EE }, {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, = MT32 }, {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, = MT32 }, diff --git a/target/mips/translate.c b/target/mips/translate.c index df69fa0e9f..2cff740bac 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4229,17 +4229,21 @@ static void gen_shift(DisasContext *ctx, uint32_t o= pc, /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { - if (reg =3D=3D 0 && (opc =3D=3D OPC_MFHI || opc =3D=3D OPC_MFLO)) { + if (reg =3D=3D 0 && (opc =3D=3D OPC_MFHI || opc =3D=3D TX79_MMI_MFHI1 = || + opc =3D=3D OPC_MFLO || opc =3D=3D TX79_MMI_MFLO1)) { /* Treat as NOP. */ return; } =20 if (acc !=3D 0) { - check_dsp(ctx); + if (!(ctx->insn_flags & INSN_R5900)) { + check_dsp(ctx); + } } =20 switch (opc) { case OPC_MFHI: + case TX79_MMI_MFHI1: #if defined(TARGET_MIPS64) if (acc !=3D 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); @@ -4250,6 +4254,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MFLO: + case TX79_MMI_MFLO1: #if defined(TARGET_MIPS64) if (acc !=3D 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); @@ -4260,6 +4265,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MTHI: + case TX79_MMI_MTHI1: if (reg !=3D 0) { #if defined(TARGET_MIPS64) if (acc !=3D 0) { @@ -4274,6 +4280,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } break; case OPC_MTLO: + case TX79_MMI_MTLO1: if (reg !=3D 0) { #if defined(TARGET_MIPS64) if (acc !=3D 0) { @@ -24658,13 +24665,17 @@ static void decode_tx79_mmi(CPUMIPSState *env, Di= sasContext *ctx) case TX79_MMI_MULTU1: gen_mul_txx9(ctx, opc, rd, rs, rt); break; + case TX79_MMI_MTLO1: + case TX79_MMI_MTHI1: + gen_HILO(ctx, opc, 1, rs); + break; + case TX79_MMI_MFLO1: + case TX79_MMI_MFHI1: + gen_HILO(ctx, opc, 1, rd); + break; case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */ case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */ case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */ - case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */ - case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */ - case TX79_MMI_MFLO1: /* TODO: TX79_MMI_MFLO1 */ - case TX79_MMI_MTLO1: /* TODO: TX79_MMI_MTLO1 */ case TX79_MMI_DIV1: /* TODO: TX79_MMI_DIV1 */ case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */ case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */ --=20 2.18.1