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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , peng guo , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL 33/75] hw/i386/pc: Avoid overlap between CXL window and PCI 64bit BARs in QEMU Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.43, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1759692116891116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: peng guo When using a CXL Type 3 device together with a virtio 9p device in QEMU on a physical server, the 9p device fails to initialize properly. The kernel rep= orts the following error: virtio: device uses modern interface but does not have VIRTIO_F_VERSION= _1 9pnet_virtio virtio0: probe with driver 9pnet_virtio failed with error = -22 Further investigation revealed that the 64-bit BAR space assigned to the 9p= net device was overlapped by the memory window allocated for the CXL devices. A= s a result, the kernel could not correctly access the BAR region, causing the virtio device to malfunction. An excerpt from /proc/iomem shows: 480010000-cffffffff : CXL Window 0 480010000-4bfffffff : PCI Bus 0000:00 4c0000000-4c01fffff : PCI Bus 0000:0c 4c0000000-4c01fffff : PCI Bus 0000:0d 4c0200000-cffffffff : PCI Bus 0000:00 4c0200000-4c0203fff : 0000:00:03.0 4c0200000-4c0203fff : virtio-pci-modern To address this issue, this patch adds the reserved memory end calculation for cxl devices to reserve sufficient address space and ensure that CXL mem= ory windows are allocated beyond all PCI 64-bit BARs. This prevents overlap with 64-bit BARs regions such as those used by virtio or other pcie devices, resolving the conflict. QEMU Build Configuration: ./configure --prefix=3D/home/work/qemu_master/build/ \ --target-list=3Dx86_64-softmmu \ --enable-kvm \ --enable-virtfs QEMU Boot Command: sudo /home/work/qemu_master/qemu/build/qemu-system-x86_64 \ -nographic -machine q35,cxl=3Don -enable-kvm -m 16G -smp 8 \ -hda /home/work/gp_qemu/rootfs.img \ -virtfs local,path=3D/home/work/gp_qemu/share,mount_tag=3Dhost0,sec= urity_model=3Dpassthrough,id=3Dhost0 \ -kernel /home/work/linux_output/arch/x86/boot/bzImage \ --append "console=3DttyS0 crashkernel=3D256M root=3D/dev/sda rootfs= type=3Dext4 rw loglevel=3D8" \ -object memory-backend-ram,id=3Dvmem0,share=3Don,size=3D4096M \ -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,sl= ot=3D2 \ -device cxl-type3,bus=3Droot_port13,volatile-memdev=3Dvmem0,id=3Dcx= l-vmem0,sn=3D0x123456789 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G Fixes: 03b39fcf64bc ("hw/cxl: Make the CXL fixed memory window setup a mach= ine parameter") Signed-off-by: peng guo Reviewed-by: Michael S. Tsirkin Message-ID: <20250805142300.15226-1-engguopeng@buaa.edu.cn> Signed-off-by: Michael S. Tsirkin --- hw/i386/pc.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index bc048a6d13..eb36d50589 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -837,6 +837,7 @@ void pc_memory_init(PCMachineState *pcms, hwaddr maxphysaddr, maxusedaddr; hwaddr cxl_base, cxl_resv_end =3D 0; X86CPU *cpu =3D X86_CPU(first_cpu); + uint64_t res_mem_end; =20 assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + x86ms->above_4g_mem_size); @@ -978,16 +979,17 @@ void pc_memory_init(PCMachineState *pcms, =20 rom_set_fw(fw_cfg); =20 - if (machine->device_memory) { - uint64_t *val =3D g_malloc(sizeof(*val)); - uint64_t res_mem_end; + if (pcms->cxl_devices_state.is_enabled) { + res_mem_end =3D cxl_resv_end; + } else if (machine->device_memory) { + res_mem_end =3D machine->device_memory->base + + memory_region_size(&machine->device_memory->mr); + } else { + res_mem_end =3D 0; + } =20 - if (pcms->cxl_devices_state.is_enabled) { - res_mem_end =3D cxl_resv_end; - } else { - res_mem_end =3D machine->device_memory->base - + memory_region_size(&machine->device_memory->mr= ); - } + if (res_mem_end) { + uint64_t *val =3D g_malloc(sizeof(*val)); *val =3D cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*va= l)); } --=20 MST