From nobody Fri May 3 09:46:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1575939171; cv=none; d=zohomail.com; s=zohoarc; b=lsAVbE943EwbhVeCwM9K2g4MAIeBOOmjRcucP6A6Ocz8dF9fxYiIy4WDF7AWNaVDlNYIfdgmOaDPrhNl7jRTDp8wg4Gfosi5vNj9SQhmfrV1r/iF/DhFki7h4rm5wJZnF2uM8iRGQp7IvXZGoap2vW1Zeikaqyu+j0VAW3ls4U4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575939171; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rUFlEnpp1XzckM6kcV2NqxDXgI9i9LAVjGAQGY512Q8=; b=BwnV1fh0U+IeBV2JzVlZyHgB2ZrYAeeEISHKVJ790Ad9CjNcNd0KOeTACTPqYnzAzy4HfSC/uOiAfppYLHJJlsTyFswctyOspANMUBIRxxiCJ91XGwdXBZb42aAcbJPenR85MvhiaFII/B+T5C9Spabed889+Ty1uuQqRuslCv8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575939171583471.7590976925545; Mon, 9 Dec 2019 16:52:51 -0800 (PST) Received: from localhost ([::1]:48810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieTli-0002nW-9z for importer@patchew.org; Mon, 09 Dec 2019 19:52:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59249) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieTkT-0001Yf-LA for qemu-devel@nongnu.org; Mon, 09 Dec 2019 19:51:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieTkS-0000N8-Ah for qemu-devel@nongnu.org; Mon, 09 Dec 2019 19:51:33 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:41529) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieTkP-0000Ll-Lf; Mon, 09 Dec 2019 19:51:29 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 0AB3B2274C; Mon, 9 Dec 2019 19:51:28 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Mon, 09 Dec 2019 19:51:28 -0500 Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id BE98B30600D4; Mon, 9 Dec 2019 19:51:25 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=rUFlEnpp1Xzck M6kcV2NqxDXgI9i9LAVjGAQGY512Q8=; b=kzpsk9a+FMdyP9JOh+u46xMxCCOWX /WJVA7FRXvTxX4shCMAb208r7cjsPxtelke/dA/6NurHBF6c3BEN3UIBtqKxrBLC x6MybfmPjyVazd3q3UjY2GPPkZoxD7V7+cFrY5jTpmllfP2/J6hqtw0HWUHxdkXo OMkrWBCy137S4mqTwMIbO18jL/Ud1cgh33BXJ6bWAazquZ8asPSPoBgIqw6J7ike 9BeBnIwcDRIPTgEAN9Zfugs0LBdugix4QPfj/+QQQ0Hh1Z6ljwU/StBTOQmCns// VH6hlN1sD+aBVz0GPaZbvSZPUbOaihM/XVZ7aEWjYvJqyWdLq3itIbimw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=rUFlEnpp1XzckM6kcV2NqxDXgI9i9LAVjGAQGY512Q8=; b=kuB49+zX TByF//kQfk8ML5iLwfoo2LgALJGu0CGBDN5gGRxO1l9z/JRHo6EdImNLORc/CYhy HKiWxi3IIT5P1XR7vTaiI2G/VUpwkyf5wLxgyfH5w2khXYU2hbcVybsC8fmHMrCS pksc3WhGOXBwybnBPxRWGzu7bXYj7g3i7V5D1eMbzee1PIBKw/Jk6+V6jLhCnqDk sa5GX7TlOIuo4SJeLBQL9tBofrAQulV50gHwFuTZ4mqTQHt544YqRYAbYHqI1MhP GxRQaoMI9gYiSQBhEnbxwfhnSGJQZ9of8WenFUQsLBy03trzYnvEl7JGi/PrvbeG 0WxkQ2aA865CQw== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelvddgvddvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomheptehnughrvgifucflvghffhgvrhihuceorghnughrvgifsegr jhdrihgurdgruheqnecukfhppedvtddvrdekuddrudekrdeftdenucfrrghrrghmpehmrg hilhhfrhhomheprghnughrvgifsegrjhdrihgurdgruhenucevlhhushhtvghrufhiiigv pedt X-ME-Proxy: From: Andrew Jeffery To: qemu-arm@nongnu.org Subject: [PATCH 1/2] hw/sd: Configure number of slots exposed by the ASPEED SDHCI model Date: Tue, 10 Dec 2019 11:22:50 +1030 Message-Id: <11e1d38d2374a48996a3496c906db215de246583.1575938234.git-series.andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.27 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, clg@kaod.org, joel@jms.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The AST2600 includes a second cut-down version of the SD/MMC controller found in the AST2500, named the eMMC controller. It's cut down in the sense that it only supports one slot rather than two, but it brings the total number of slots supported by the AST2600 to three. The existing code assumed that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/aspeed.c | 2 +- hw/arm/aspeed_ast2600.c | 2 ++ hw/arm/aspeed_soc.c | 3 +++ hw/sd/aspeed_sdhci.c | 11 +++++++++-- include/hw/sd/aspeed_sdhci.h | 1 + 5 files changed, 16 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 028191ff36fc..862549b1f3a9 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -259,7 +259,7 @@ static void aspeed_board_init(MachineState *machine, cfg->i2c_init(bmc); } =20 - for (i =3D 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { + for (i =3D 0; i < bmc->soc.sdhci.num_slots; i++) { SDHCIState *sdhci =3D &bmc->soc.sdhci.slots[i]; DriveInfo *dinfo =3D drive_get_next(IF_SD); BlockBackend *blk; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931887ac681f..931ee5aae183 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -208,6 +208,8 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); =20 + object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abor= t); + /* Init sd card slot class here so that they're under the correct pare= nt */ for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index f4fe243458fd..3498f55603f2 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -215,6 +215,9 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), TYPE_ASPEED_SDHCI); =20 + object_property_set_int(OBJECT(&s->sdhci), ASPEED_SDHCI_NUM_SLOTS, + "num-slots", &error_abort); + /* Init sd card slot class here so that they're under the correct pare= nt */ for (i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index cff3eb7dd21e..939d1510dedb 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/irq.h" #include "migration/vmstate.h" +#include "hw/qdev-properties.h" =20 #define ASPEED_SDHCI_INFO 0x00 #define ASPEED_SDHCI_INFO_RESET 0x00030000 @@ -120,14 +121,14 @@ static void aspeed_sdhci_realize(DeviceState *dev, Er= ror **errp) =20 /* Create input irqs for the slots */ qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, - sdhci, NULL, ASPEED_SDHCI_NUM_SLOT= S); + sdhci, NULL, sdhci->num_slots); =20 sysbus_init_irq(sbd, &sdhci->irq); memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, sdhci, TYPE_ASPEED_SDHCI, 0x1000); sysbus_init_mmio(sbd, &sdhci->iomem); =20 - for (int i =3D 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { + for (int i =3D 0; i < sdhci->num_slots; ++i) { Object *sdhci_slot =3D OBJECT(&sdhci->slots[i]); SysBusDevice *sbd_slot =3D SYS_BUS_DEVICE(&sdhci->slots[i]); =20 @@ -174,6 +175,11 @@ static const VMStateDescription vmstate_aspeed_sdhci = =3D { }, }; =20 +static Property aspeed_sdhci_properties[] =3D { + DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) { DeviceClass *dc =3D DEVICE_CLASS(classp); @@ -181,6 +187,7 @@ static void aspeed_sdhci_class_init(ObjectClass *classp= , void *data) dc->realize =3D aspeed_sdhci_realize; dc->reset =3D aspeed_sdhci_reset; dc->vmsd =3D &vmstate_aspeed_sdhci; + dc->props =3D aspeed_sdhci_properties; } =20 static TypeInfo aspeed_sdhci_info =3D { diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h index dfdab4379021..dffbb46946b9 100644 --- a/include/hw/sd/aspeed_sdhci.h +++ b/include/hw/sd/aspeed_sdhci.h @@ -24,6 +24,7 @@ typedef struct AspeedSDHCIState { SysBusDevice parent; =20 SDHCIState slots[ASPEED_SDHCI_NUM_SLOTS]; + uint8_t num_slots; =20 MemoryRegion iomem; qemu_irq irq; --=20 git-series 0.9.1 From nobody Fri May 3 09:46:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1575939242; cv=none; d=zohomail.com; s=zohoarc; b=H7gwzhVmLYiMtElH9a1fHdVK973+yEFkV/8SDmm0NXrAFuptRSPm0zfHO9jX5Yi9bNmebgg6uNoeJJz6PetBlgqSQkUazZMTfri83QW6ffx30T7EWeaLZuJ17/VMB5ReBso6kYS6SFQCxx6q8dcs4cF0szMn/ONoM0yOvvC6Rbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1575939242; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H0aPY86yzeMQwfYD+h2g47JaRugDPvF0iktz1Pvolmc=; b=QT4nhyzsFhtCB7jelw3RDh4N3Q6znePuqic3wS5YnouwuoUIAaWNpUffSh1wh1GtsMVplgCs4VOx9DnUiQCRH864XkD2SOm/sNSvJI8z99hf344HQqmcWNLN85q9nj4PUFgRv6M5cOG1RMS0xITwoojolbyZb5Dg7zBMxVi83Rk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1575939241998907.723768120803; Mon, 9 Dec 2019 16:54:01 -0800 (PST) Received: from localhost ([::1]:48832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieTmq-0004HK-Q5 for importer@patchew.org; Mon, 09 Dec 2019 19:54:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59262) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ieTkU-0001aE-NF for qemu-devel@nongnu.org; Mon, 09 Dec 2019 19:51:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ieTkT-0000NY-GG for qemu-devel@nongnu.org; Mon, 09 Dec 2019 19:51:34 -0500 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:54371) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ieTkR-0000MU-1G; Mon, 09 Dec 2019 19:51:31 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id AF6FA22721; Mon, 9 Dec 2019 19:51:30 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Mon, 09 Dec 2019 19:51:30 -0500 Received: from mistburn.au.ibm.com (bh02i525f01.au.ibm.com [202.81.18.30]) by mail.messagingengine.com (Postfix) with ESMTPA id 7283330600BD; Mon, 9 Dec 2019 19:51:28 -0500 (EST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm1; bh=H0aPY86yzeMQw fYD+h2g47JaRugDPvF0iktz1Pvolmc=; b=O67l5jMSiTknwr7IuFdXeQWoXPUdx pK4aDoyNDWGySxtClZwH5gXLTkZeen0M9BS9vMgFHLmaEjpvWTWZQid7s6nQzB0A Yna28SH/w2Q5X6xSFVwF2yQ/rjg4fJm/KdFAZ32BxnHkXZIkpfKbhJWxhTwX1JSS U9C/IfSHtHYIHF3jDkqPTaKhoZa2JDJAwJzQtylu3W8j0RvMvQqjDKk0JDCK2I8M ldz2/ze4JcIh2Cw3JP/1fJc6C80HEaCf2D78j9nGB+t65miQa4/eu03G0trjkF61 yjPEKHIGGMWE9V4aOMH7tZj4P51glUXlyim8cN6SwhG10MRaKF+bSf4xA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=H0aPY86yzeMQwfYD+h2g47JaRugDPvF0iktz1Pvolmc=; b=B4ZmFT+A h6pTMgQJGXBRbwvM6zN3HCl+xREwwAgXeU+pzNQxJ71zfumn4wEuf6NjRE4KjvUk ciaxH27yfuzEAI2hjSeFXQU3HmbkMGZWSicNVuy/savCzE9YbCD7m5+9yFC2C67u 0WOMXowkXIhAq68ZnkrM/JSwEcnyopRSXdqAcAFobmHdzyvqd+P0uHav6V9xDj0M CAdhuLiWwd1FNRhiTlmFJTlsfD8/wEuPKgm42saNNGH2rU27GgrgENOWmztvsW6b ENfdRuho0fs2JF60s/OjxvAfwsBohRV5w+ZkxiS1AmtXm4KrQRaYyGE9ovn1FDzT tYW08B3T+FNr/A== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelvddgvddvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhgggfestdekre dtredttdenucfhrhhomheptehnughrvgifucflvghffhgvrhihuceorghnughrvgifsegr jhdrihgurdgruheqnecukfhppedvtddvrdekuddrudekrdeftdenucfrrghrrghmpehmrg hilhhfrhhomheprghnughrvgifsegrjhdrihgurdgruhenucevlhhushhtvghrufhiiigv pedu X-ME-Proxy: From: Andrew Jeffery To: qemu-arm@nongnu.org Subject: [PATCH 2/2] hw/arm: ast2600: Wire up the eMMC controller Date: Tue, 10 Dec 2019 11:22:51 +1030 Message-Id: <5a93d2f9d375f92e9db6b1cf8687f86beaedcbb2.1575938234.git-series.andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.27 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, clg@kaod.org, joel@jms.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Initialise another SDHCI model instance for the AST2600's eMMC controller and use the SDHCI's num_slots value introduced previously to determine whether we should create an SD card instance for the new slot. Signed-off-by: Andrew Jeffery --- hw/arm/aspeed.c | 13 +++++++++++++ hw/arm/aspeed_ast2600.c | 21 +++++++++++++++++++++ include/hw/arm/aspeed_soc.h | 2 ++ 3 files changed, 36 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 862549b1f3a9..0e08d62e9ff3 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -272,6 +272,19 @@ static void aspeed_board_init(MachineState *machine, object_property_set_bool(OBJECT(card), true, "realized", &error_fa= tal); } =20 + if (bmc->soc.emmc.num_slots) { + SDHCIState *emmc =3D &bmc->soc.emmc.slots[0]; + DriveInfo *dinfo =3D drive_get_next(IF_SD); + BlockBackend *blk; + DeviceState *card; + + blk =3D dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + card =3D qdev_create(qdev_get_child_bus(DEVICE(emmc), "sd-bus"), + TYPE_SD_CARD); + qdev_prop_set_drive(card, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(card), true, "realized", &error_fa= tal); + } + arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); } =20 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 931ee5aae183..723c8196c8a5 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -46,6 +46,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { [ASPEED_ADC] =3D 0x1E6E9000, [ASPEED_VIDEO] =3D 0x1E700000, [ASPEED_SDHCI] =3D 0x1E740000, + [ASPEED_EMMC] =3D 0x1E750000, [ASPEED_GPIO] =3D 0x1E780000, [ASPEED_GPIO_1_8V] =3D 0x1E780800, [ASPEED_RTC] =3D 0x1E781000, @@ -64,6 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { =20 #define ASPEED_SOC_AST2600_MAX_IRQ 128 =20 +/* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ static const int aspeed_soc_ast2600_irqmap[] =3D { [ASPEED_UART1] =3D 47, [ASPEED_UART2] =3D 48, @@ -77,6 +79,7 @@ static const int aspeed_soc_ast2600_irqmap[] =3D { [ASPEED_ADC] =3D 78, [ASPEED_XDMA] =3D 6, [ASPEED_SDHCI] =3D 43, + [ASPEED_EMMC] =3D 15, [ASPEED_GPIO] =3D 40, [ASPEED_GPIO_1_8V] =3D 11, [ASPEED_RTC] =3D 13, @@ -215,6 +218,14 @@ static void aspeed_soc_ast2600_init(Object *obj) sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI= ); } + + sysbus_init_child_obj(obj, "emmc", OBJECT(&s->emmc), sizeof(s->emmc), + TYPE_ASPEED_SDHCI); + + object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort= ); + + sysbus_init_child_obj(obj, "emmc[*]", OBJECT(&s->emmc.slots[0]), + sizeof(s->emmc.slots[0]), TYPE_SYSBUS_SDHCI); } =20 /* @@ -487,6 +498,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) sc->memmap[ASPEED_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_SDHCI)); + + /* eMMC */ + object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, + aspeed_soc_get_irq(s, ASPEED_EMMC)); } =20 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 495c08be1b84..911443f4c071 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -56,6 +56,7 @@ typedef struct AspeedSoCState { AspeedGPIOState gpio; AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; + AspeedSDHCIState emmc; } AspeedSoCState; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -125,6 +126,7 @@ enum { ASPEED_MII4, ASPEED_SDRAM, ASPEED_XDMA, + ASPEED_EMMC, }; =20 #endif /* ASPEED_SOC_H */ --=20 git-series 0.9.1