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The host controller shall abort all active transfers, return internal state machines to idle, and de-assert all interrupts. Currently, QEMU's UFS emulator only clears HCS and HCE registers upon HCE=3D0, leaving internal state active. Specifically: - Outstanding SCSI requests in the block layer are not purged. - Active bottom halves (doorbell_bh, complete_bh, and MCQ sq/cq BHs) remain scheduled. - Allocated MCQ Submission and Completion Queues (sq and cq) are not freed. - Dynamic MCQ queue registers, legacy UTRL request states, and status registers (UTRLCNR, UTRLRSR) remain stale. Implement ufs_hce_reset() to: 1. Implement .cancel callback in ufs_scsi_info to properly unref scsi_req and prevent reference leaks when SCSI requests are purged. 2. Cancel active bottom halves (doorbell_bh, complete_bh, and MCQ sq/cq BHs) and guard them with a resetting flag before purging requests, ensuring blk_drain() cannot run or reschedule request-producing BHs. 3. Purge outstanding SCSI requests for all logical units via scsi_device_purge_requests(). 4. Clear standard request list slots and release SGLs via ufs_clear_req(), and clear doorbells and status registers (UTRLCNR, UTRLRSR). 5. Free allocated MCQ queues and clear dynamic queue registers while preserving static capability offsets. 6. De-assert interrupts via ufs_irq_check(). 7. Add a trace_ufs_hce_reset() trace event. Signed-off-by: Stanley Jhu Reviewed-by: Jeuk Kim Signed-off-by: Jeuk Kim --- hw/ufs/lu.c | 7 ++++ hw/ufs/trace-events | 1 + hw/ufs/ufs.c | 96 ++++++++++++++++++++++++++++++++++++++++++++- hw/ufs/ufs.h | 2 + 4 files changed, 105 insertions(+), 1 deletion(-) diff --git a/hw/ufs/lu.c b/hw/ufs/lu.c index eeca865eb5..bdb1650851 100644 --- a/hw/ufs/lu.c +++ b/hw/ufs/lu.c @@ -188,6 +188,12 @@ static void ufs_scsi_command_complete(SCSIRequest *scs= i_req, size_t resid) scsi_req_unref(scsi_req); } =20 +static void ufs_scsi_command_cancelled(SCSIRequest *scsi_req) +{ + scsi_req->hba_private =3D NULL; + scsi_req_unref(scsi_req); +} + static QEMUSGList *ufs_get_sg_list(SCSIRequest *scsi_req) { UfsRequest *req =3D scsi_req->hba_private; @@ -202,6 +208,7 @@ static const struct SCSIBusInfo ufs_scsi_info =3D { =20 .get_sg_list =3D ufs_get_sg_list, .complete =3D ufs_scsi_command_complete, + .cancel =3D ufs_scsi_command_cancelled, }; =20 static int ufs_emulate_report_luns(UfsRequest *req, uint8_t *outbuf, diff --git a/hw/ufs/trace-events b/hw/ufs/trace-events index 0cd3ba9b02..922293355b 100644 --- a/hw/ufs/trace-events +++ b/hw/ufs/trace-events @@ -14,6 +14,7 @@ ufs_process_uiccmd(uint32_t uiccmd, uint32_t ucmdarg1, ui= nt32_t ucmdarg2, uint32 ufs_mcq_complete_req(uint8_t qid) "sqid %"PRIu8"" ufs_mcq_create_sq(uint8_t sqid, uint8_t cqid, uint64_t addr, uint16_t size= ) "mcq create sq sqid %"PRIu8", cqid %"PRIu8", addr 0x%"PRIx64", size %"PRI= u16"" ufs_mcq_create_cq(uint8_t cqid, uint64_t addr, uint16_t size) "mcq create = cq cqid %"PRIu8", addr 0x%"PRIx64", size %"PRIu16"" +ufs_hce_reset(void) "HCE 1 -> 0 reset: cancelling BHs, resetting MCQ and r= equest lists" =20 # error condition ufs_err_dma_read_utrd(uint32_t slot, uint64_t addr) "failed to read utrd. = UTRLDBR slot %"PRIu32", UTRD dma addr %"PRIu64"" diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index 160a4ac4f3..3c4d7424da 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/ufs.c @@ -452,6 +452,10 @@ static void ufs_mcq_process_sq(void *opaque) uint16_t head =3D ufs_mcq_sq_head(u, sq->sqid); int err; =20 + if (u->resetting) { + return; + } + while (!(ufs_mcq_sq_empty(u, sq->sqid) || QTAILQ_EMPTY(&sq->req_list))= ) { addr =3D sq->addr + head; err =3D ufs_addr_read(sq->u, addr, (void *)&sqe, sizeof(sqe)); @@ -525,7 +529,7 @@ static void ufs_mcq_process_cq(void *opaque) tail =3D (tail + sizeof(req->cqe)) % (cq->size * sizeof(req->cqe)); ufs_mcq_update_cq_tail(u, cq->cqid, tail); =20 - if (QTAILQ_EMPTY(&req->sq->req_list) && + if (!u->resetting && QTAILQ_EMPTY(&req->sq->req_list) && !ufs_mcq_sq_empty(u, req->sq->sqid)) { /* Dequeueing from SQ was blocked due to lack of free requests= */ qemu_bh_schedule(req->sq->bh); @@ -722,6 +726,87 @@ static bool ufs_mcq_delete_cq(UfsHc *u, uint8_t qid) return true; } =20 +static void ufs_hce_reset(UfsHc *u) +{ + int i; + + trace_ufs_hce_reset(); + + u->resetting =3D true; + + /* 1. Cancel active Bottom Halves before purging requests */ + if (u->doorbell_bh) { + qemu_bh_cancel(u->doorbell_bh); + } + if (u->complete_bh) { + qemu_bh_cancel(u->complete_bh); + } + if (u->params.mcq) { + for (i =3D 0; i < ARRAY_SIZE(u->sq); i++) { + if (u->sq[i] && u->sq[i]->bh) { + qemu_bh_cancel(u->sq[i]->bh); + } + } + for (i =3D 0; i < ARRAY_SIZE(u->cq); i++) { + if (u->cq[i] && u->cq[i]->bh) { + qemu_bh_cancel(u->cq[i]->bh); + } + } + } + + /* 2. Purge outstanding SCSI requests for all logical units */ + for (i =3D 0; i < UFS_MAX_LUS; i++) { + if (u->lus[i] && u->lus[i]->scsi_dev) { + scsi_device_purge_requests(u->lus[i]->scsi_dev, SENSE_CODE(RES= ET)); + } + } + + /* 3. Reset standard request list slots, doorbells, and status registe= rs */ + for (i =3D 0; i < u->params.nutrs; i++) { + ufs_clear_req(&u->req_list[i]); + u->req_list[i].state =3D UFS_REQUEST_IDLE; + } + u->reg.utrldbr =3D 0; + u->reg.utmrldbr =3D 0; + u->reg.utrlcnr =3D 0; + u->reg.utrlrsr =3D 0; + u->reg.is =3D 0; + + /* 4. Free MCQ Queues and reset MCQ dynamic registers */ + if (u->params.mcq) { + for (i =3D 0; i < ARRAY_SIZE(u->sq); i++) { + if (u->sq[i]) { + ufs_mcq_free_sq(u->sq[i]); + u->sq[i] =3D NULL; + } + } + for (i =3D 0; i < ARRAY_SIZE(u->cq); i++) { + if (u->cq[i]) { + ufs_mcq_free_cq(u->cq[i]); + u->cq[i] =3D NULL; + } + } + + /* Clear dynamic queue configuration registers without overwriting= static capability offsets */ + for (i =3D 0; i < ARRAY_SIZE(u->mcq_reg); i++) { + u->mcq_reg[i].sqattr =3D 0; + u->mcq_reg[i].sqlba =3D 0; + u->mcq_reg[i].squba =3D 0; + u->mcq_reg[i].sqcfg =3D 0; + u->mcq_reg[i].cqattr =3D 0; + u->mcq_reg[i].cqlba =3D 0; + u->mcq_reg[i].cquba =3D 0; + u->mcq_reg[i].cqcfg =3D 0; + } + memset(u->mcq_op_reg, 0, sizeof(u->mcq_op_reg)); + } + + u->resetting =3D false; + + /* 5. De-assert IRQ */ + ufs_irq_check(u); +} + static void ufs_write_reg(UfsHc *u, hwaddr offset, uint32_t data, unsigned= size) { switch (offset) { @@ -739,6 +824,7 @@ static void ufs_write_reg(UfsHc *u, hwaddr offset, uint= 32_t data, unsigned size) u->reg.hce =3D FIELD_DP32(u->reg.hce, HCE, HCE, 1); } else if (FIELD_EX32(u->reg.hce, HCE, HCE) && !FIELD_EX32(data, HCE, HCE)) { + ufs_hce_reset(u); u->reg.hcs =3D 0; u->reg.hce =3D FIELD_DP32(u->reg.hce, HCE, HCE, 0); } @@ -2089,6 +2175,10 @@ static void ufs_process_req(void *opaque) UfsRequest *req; int slot; =20 + if (u->resetting) { + return; + } + for (slot =3D 0; slot < u->params.nutrs; slot++) { req =3D &u->req_list[slot]; =20 @@ -2115,6 +2205,10 @@ void ufs_complete_req(UfsRequest *req, UfsReqResult = req_result) =20 req->state =3D UFS_REQUEST_COMPLETE; =20 + if (u->resetting) { + return; + } + if (ufs_mcq_req(req)) { trace_ufs_mcq_complete_req(req->sq->sqid); QTAILQ_INSERT_TAIL(&req->sq->cq->req_list, req, entry); diff --git a/hw/ufs/ufs.h b/hw/ufs/ufs.h index aa8361d93d..6f2693b7ca 100644 --- a/hw/ufs/ufs.h +++ b/hw/ufs/ufs.h @@ -173,6 +173,8 @@ typedef struct UfsHc { UfsSq *sq[UFS_MAX_MCQ_QNUM]; UfsCq *cq[UFS_MAX_MCQ_QNUM]; =20 + bool resetting; + /* Extended features */ UfsWb wb; =20 --=20 2.43.0