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Sat, 25 Jul 2026 09:52:32 -0700 (PDT) From: lanxiaoyun To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Alistair.Francis@wdc.com, palmer@dabbelt.com, lanxiaoyun1 Subject: [PATCH v1 1/1] hw/intc: resample level IRQ on PLIC completion Date: Sun, 26 Jul 2026 00:51:18 +0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=dubdublan1987@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 25 Jul 2026 14:38:33 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785004776539154100 Content-Type: text/plain; charset="utf-8" From: lanxiaoyun1 When an interrupt completion message is received, if the interrupt is level-triggered and still asserted, forward a new interrupt request to the PLIC core. This updates the SiFive PLIC IRQ handling so completion rechecks the current source level and reasserts pending state when the input remains high, matching the RISC-V PLIC specification. Signed-off-by: lanxiaoyun1 --- hw/intc/sifive_plic.c | 4 +++- include/hw/intc/sifive_plic.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 9c84ff06a9..43f235e329 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -246,6 +246,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr= , uint64_t value, } else if (contextid =3D=3D 4) { if (value < plic->num_sources) { sifive_plic_set_claimed(plic, value, false); + sifive_plic_set_pending(plic, value, !!plic->source[value]= ); sifive_plic_update(plic); } } else { @@ -276,6 +277,7 @@ static void sifive_plic_reset(DeviceState *dev) int i; =20 memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources); + memset(s->source, 0, sizeof(uint32_t) * s->num_sources); memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs); memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words); memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words); @@ -353,7 +355,7 @@ static void parse_hart_config(SiFivePLICState *plic) static void sifive_plic_irq_request(void *opaque, int irq, int level) { SiFivePLICState *s =3D opaque; - + s->source[irq] =3D !!level; if (level > 0) { sifive_plic_set_pending(s, irq, true); sifive_plic_update(s); diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h index 32973dbf28..627a418ba1 100644 --- a/include/hw/intc/sifive_plic.h +++ b/include/hw/intc/sifive_plic.h @@ -54,6 +54,7 @@ struct SiFivePLICState { uint32_t num_enables; PLICAddr *addr_config; uint32_t *source_priority; + uint32_t *source; uint32_t *target_priority; uint32_t *pending; uint32_t *claimed; --=20 2.43.0